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Methods of forming a semiconductor device with low-k spacers and the resulting device
X Cai, R Xie, X Zhang
US Patent 9,064,948, 2015
Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
R Xie, X Cai, X Zhang
US Patent 9,190,486, 2015
Silicide protection during contact metallization and resulting semiconductor structures
VK Kamineni, R Xie, R Miller
US Patent 9,111,907, 2015
Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
X Cai, R Xie, A Khakifirooz, K Cheng
US Patent 8,921,191, 2014
Multi-channel gate-all-around FET
Q Liu, R Xie, C Yeh, X Cai
US Patent 9,502,518, 2016
FinFET semiconductor devices with improved source/drain resistance and methods of making same
R Xie, M Raymond, R Miller
US Patent 9,147,765, 2015
Effects of sulfur passivation on germanium MOS capacitors with HfON gate dielectric
R Xie, C Zhu
IEEE electron device letters 28 (11), 976-979, 2007
High- gate stack on germanium substrate with fluorine incorporation
R Xie, M Yu, MY Lai, L Chan, C Zhu
Applied physics letters 92 (16), 163505, 2008
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ...
2016 IEEE International Electron Devices Meeting (IEDM), 2.7. 1-2.7. 4, 2016
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ...
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
Methods of Forming Replacement Gate Structures for Semiconductor Devices
R Xie, X Cai, R Miller, A Knorr
US Patent App. 13/354,844, 2013
Defect-free strain relaxed buffer layer
P Morin, K Cheng, J Fronheiser, X Cai, J Li, S Mochizuki, R Xie, H He, ...
US Patent App. 14/588,221, 2016
Formation of the dielectric cap layer for a replacement gate structure
R Xie, BP Haran, DV Horak, SC Fan
US Patent 8,772,168, 2014
Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products
R Xie, K Lim, MG Sung, RRH Kim
US Patent 9,412,616, 2016
Interface-Engineered High-Mobility High-/Ge pMOSFETs With 1-nm Equivalent Oxide Thickness
R Xie, TH Phung, W He, M Yu, C Zhu
IEEE transactions on electron devices 56 (6), 1330-1337, 2009
High mobility high-k/Ge pMOSFETs with 1 nm EOT-new concept on interface engineering and interface characterization
R Xie, TH Phung, W He, Z Sun, M Yu, Z Cheng, C Zhu
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Effects of fluorine incorporation and forming gas annealing on high- gated germanium metal-oxide-semiconductor with surface passivation
R Xie, W He, M Yu, C Zhu
Applied Physics Letters 93 (7), 073504, 2008
Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices
R Xie, X Cai, K Cheng, A Khakifirooz
US Patent 9,236,480, 2016
Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
R Xie, X Cai, K Cheng, A Khakifirooz
US Patent 9,153,498, 2015
Methods of forming replacement gate structures for transistors and the resulting devices
R Xie, K Choi, SC Fan, S Ponoth
US Patent 9,257,348, 2016
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