Matt Farrens
Matt Farrens
Verified email at
Cited by
Cited by
A modified approach to data cache management
G Tyson, M Farrens, J Matthews, AR Pleszkun
Proceedings of the 28th annual international symposium on Microarchitecture …, 1995
HLS: Combining statistical and symbolic simulation to guide microprocessor designs
M Oskin, FT Chong, M Farrens
ACM SIGARCH Computer Architecture News 28 (2), 71-82, 2000
Eager writeback-a technique for improving bandwidth utilization
HHS Lee, GS Tyson, MK Farrens
Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000
Addressing system-level trimming issues in on-chip nanophotonic networks
C Nitta, M Farrens, V Akella
2011 IEEE 17th International Symposium on High Performance Computer …, 2011
Dynamic base register caching: A technique for reducing address bus width
M Farrens, A Park
ACM SIGARCH Computer Architecture News 19 (3), 128-137, 1991
Utilizing reuse information in data cache management
JA Rivers, ES Tam, GS Tyson, ES Davidson, M Farrens
Proceedings of the 12th international conference on Supercomputing, 449-456, 1998
Simultaneously reducing latency and power consumption in openflow switches
PT Congdon, P Mohapatra, M Farrens, V Akella
IEEE/ACM Transactions On Networking 22 (3), 1007-1020, 2013
Strategies for achieving improved processor throughput
MK Farrens, AR Pleszkun
Proceedings of the 18th annual international symposium on Computer …, 1991
Branch transition rate: A new metric for improved branch classification analysis
M Haungs, P Sallee, M Farrens
Proceedings Sixth International Symposium on High-Performance Computer …, 2000
Limited dual path execution
G Tyson, K Lick, M Farrens
Technical Report CSE-TR 346-97, University of Michigan, 1997
A study of single-chip processor/cache organizations for large numbers of transistors
M Farrens, G Tyson, AR Pleszkun
ACM SIGARCH Computer Architecture News 22 (2), 338-347, 1994
MISC: A multiple instruction stream computer
G Tyson, M Farrens, AR Pleszkun
ACM SIGMICRO Newsletter 23 (1-2), 193-196, 1992
Improving performance of small on-chip instruction caches
MK Farrens, R Pleszkun
ACM SIGARCH Computer Architecture News 17 (3), 234-241, 1989
A comparision of superscalar and decoupled access/execute architectures
MK Farrens, P Ng, P Nico
Proceedings of the 26th annual International Symposium on Microarchitecture …, 1993
Implementation of the pipe processor
MK Farrens, AR Pleszhun
Computer 24 (1), 65-70, 1991
Resilient microring resonator based photonic networks
CJ Nitta, MK Farrens, V Akella
Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011
Cache-aware affinitization on commodity multicores for high-speed network flows
V Ahuja, M Farrens, D Ghosal
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking …, 2012
Exploiting ilp in page-based intelligent memory
M Oskin, J Hensley, D Keen, FT Chong, M Farrens, A Chopra
MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999
Address compression through base register caching
A Park, M Farrens
[1990] Proceedings of the 23rd Annual Workshop and Symposium@ m_MICRO 23 …, 1990
On-chip photonic interconnects: A computer architect's perspective
CJ Nitta, M Farrens, V Akella
Springer Nature, 2022
The system can't perform the operation now. Try again later.
Articles 1–20