Michael Schulte
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Truncated multiplication with correction constant [for DSP]
MJ Schulte, EE Swartzlander
Proceedings of IEEE Workshop on VLSI Signal Processing, 388-396, 1993
2851993
An overview of reconfigurable hardware in embedded systems
P Garcia, K Compton, M Schulte, E Blem, W Fu
EURASIP Journal on Embedded Systems 2006 (1), 1-19, 2006
1902006
Approximating elementary functions with symmetric bipartite tables
MJ Schulte, JE Stine
IEEE Transactions on Computers 48 (8), 842-847, 1999
1851999
The case for GPGPU spatial multitasking
JT Adriaens, K Compton, NS Kim, MJ Schulte
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
1812012
Decimal multiplication via carry-save addition
MA Erle, MJ Schulte
Proceedings IEEE International Conference on Application-Specific Systems …, 2003
1782003
The symmetric table addition method for accurate function approximation
JE Stine, MJ Schulte
Journal of VLSI signal processing systems for signal, image and video …, 1999
1491999
Decimal multiplication with efficient partial product generation
MA Erle, EM Schwarz, MJ Schulte
17th IEEE Symposium on Computer Arithmetic (ARITH'05), 21-28, 2005
1372005
Hardware designs for exactly rounded elementary functions
MJ Schulte, EE Swartzlander
IEEE Transactions on Computers 43 (8), 964-973, 1994
1371994
High-speed multioperand decimal adders
RD Kenney, MJ Schulte
IEEE Transactions on Computers 54 (8), 953-963, 2005
1302005
Reduced power dissipation through truncated multiplication
MJ Schulte, JE Stine, JG Jansen
Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 61-69, 1999
1101999
Symmetric bipartite tables for accurate function approximation
MJ Schulte, JE Stine
Proceedings 13th IEEE Sympsoium on Computer Arithmetic, 175-183, 1997
1041997
Analysis of column compression multipliers
KC Bickerstaff, EE Swartzlander, MJ Schulte
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, 33-39, 2001
982001
Improving throughput of power-constrained GPUs using dynamic voltage/frequency and core scaling
J Lee, V Sathisha, M Schulte, K Compton, NS Kim
2011 International Conference on Parallel Architectures and Compilation …, 2011
962011
A high-frequency decimal multiplier
RD Kenney, MJ Schulte, MA Erle
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
952004
A family of variable-precision interval arithmetic processors
MJ Schulte, EE Swartzlander
IEEE Transactions on Computers 49 (5), 387-397, 2000
892000
Reduced area multipliers
KAC Bickerstaff, M Schulte, EE Swartzlander
Proceedings of International Conference on Application Specific Array …, 1993
861993
Power management system and method for a processor
JM O'connor, J Lee, M Schulte, S Manne
US Patent App. 13/628,720, 2014
822014
Parallel reduced area multipliers
CB K'andrea, MJ Schulte, EE Swartzlander
Journal of VLSI signal processing systems for signal, image and video …, 1995
781995
Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads
V Sathish, MJ Schulte, NS Kim
2012 21st International Conference on Parallel Architectures and Compilation …, 2012
772012
The sandbridge sb3011 platform
J Glossner, D Iancu, M Moudgill, G Nacer, S Jinturkar, S Stanley, ...
EURASIP journal on embedded systems 2007, 1-16, 2007
772007
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