Michael A. Kochte
Michael A. Kochte
Numascale AS, prev. Univ. Stuttgart Germany
Adresse e-mail validée de iti.uni-stuttgart.de
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Overview of the IBM Blue Gene/P project
G Almasi, S Asaad, RE Bellofatto, HR Bickford, MA Blumrich, B Brezzo, ...
IBM Journal of Research and Development 52 (1-2), 199-220, 2008
1862008
System and method for executing compute-intensive database user-defined programs on an attached high-performance parallel computer
R Natarajan, M Kochte
US Patent 7,885,969, 2011
682011
System and method for executing compute-intensive database user-defined programs on an attached high-performance parallel computer
R Natarajan, M Kochte
US Patent 7,885,969, 2011
682011
Efficient fault simulation on many-core processors
MA Kochte, M Schaal, HJ Wunderlich, CG Zoellin
Proceedings of the 47th Design Automation Conference, 380-385, 2010
572010
Fine-grained access management in reconfigurable scan networks
R Baranowski, MA Kochte, HJ Wunderlich
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
432015
Modeling, verification and pattern generation for reconfigurable scan networks
R Baranowski, MA Kochte, HJ Wunderlich
2012 IEEE International Test Conference, 1-9, 2012
402012
Concurrent self-test with partially specified patterns for low test latency and overhead
MA Kochte, CG Zoellin, HJ Wunderlich
2009 14th IEEE European Test Symposium, 53-58, 2009
402009
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures
H Zhang, L Bauer, MA Kochte, E Schneider, C Braun, ME Imhof, ...
2013 IEEE International Test Conference (ITC), 1-10, 2013
382013
Power-aware test generation with guaranteed launch safety for at-speed scan testing
X Wen, K Enokimoto, K Miyase, Y Yamato, MA Kochte, S Kajihara, ...
29th VLSI Test Symposium, 166-171, 2011
362011
Reconfigurable scan networks: Modeling, verification, and optimal pattern generation
R Baranowski, MA Kochte, HJ Wunderlich
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (2), 30, 2015
302015
Test Strategies for Reliable Runtime Reconfigurable Architectures
L Bauer, C Braun, ME Imhof, MA Kochte, E Schneider, H Zhang, J Henkel, ...
IEEE Transactions on Computers, 1, 2013
302013
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience
A Herkersdorf, H Aliee, M Engel, M Glaß, C Gimmler-Dumont, J Henkel, ...
Microelectronics Reliability 54 (6-7), 1066-1074, 2014
282014
FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects
S Hellebrand, T Indlekofer, M Kampmann, MA Kochte, C Liu, ...
2014 International Test Conference, 1-8, 2014
272014
Scan pattern retargeting and merging with reduced access time
R Baranowski, MA Kochte, HJ Wunderlich
2013 18th IEEE European Test Symposium (ETS), 1-7, 2013
272013
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures
H Zhang, MA Kochte, E Schneider, L Bauer, HJ Wunderlich, J Henkel
Proceedings of the IEEE/ACM International Conference on Computer-Aided …, 2015
232015
Securing access to reconfigurable scan networks
R Baranowski, MA Kochte, HJ Wunderlich
2013 22nd Asian Test Symposium, 295-300, 2013
232013
A novel scan segmentation design method for avoiding shift timing failure in scan testing
Y Yamato, X Wen, MA Kochte, K Miyase, S Kajihara, LT Wang
2011 IEEE International Test Conference, 1-8, 2011
222011
GPU-Accelerated Simulation of Small Delay Faults
E Schneider, MA Kochte, S Holst, X Wen, HJ Wunderlich
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
212017
GPU-accelerated small delay fault simulation
E Schneider, S Holst, MA Kochte, X Wen, HJ Wunderlich
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
202015
GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems
H Zhang, MA Kochte, ME Imhof, L Bauer, HJ Wunderlich, J Henkel
Proceedings of the The 51st Annual Design Automation Conference on Design …, 2014
202014
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