Dennis Han Chung Lin
Dennis Han Chung Lin
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Leakage current and breakdown electric-field studies on ultrathin atomic-layer-deposited on GaAs
HC Lin, PD Ye, GD Wilk
Applied physics letters 87 (18), 182904, 2005
2572005
Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Depositedas Gate Dielectric
Y Xuan, YQ Wu, HC Lin, T Shen, DY Peide
IEEE Electron Device Letters 28 (11), 935-938, 2007
2172007
Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited AI2O3 gate dielectric
Y Xuan, HC Lin, PD Ye, GD Wilk
APPLIED PHYSICS LETTERS 88, 263518, 2006
2032006
Germanium surface passivation and atomic layer deposition of high-k dielectrics—A tutorial review on Ge-based MOS capacitors
Q Xie, S Deng, M Schaekers, D Lin, M Caymax, A Delabie, XP Qu, ...
Semiconductor Science and Technology 27 (7), 074012, 2012
1522012
Simplified Surface Preparation for GaAs Passivation Using Atomic Layer-Deposited High- Dielectrics
Y Xuan, HC Lin, DY Peide
IEEE Transactions on Electron Devices 54 (8), 1811-1817, 2007
1232007
Electrical study of sulfur passivated In0. 53Ga0. 47As MOS capacitor and transistor with ALD Al2O3 as gate insulator
HC Lin, WE Wang, G Brammertz, M Meuris, M Heyns
Microelectronic Engineering 86 (7-9), 1554-1557, 2009
1162009
On the interface state density at /oxide interfaces
G Brammertz, HC Lin, M Caymax, M Meuris, M Heyns, M Passlack
Applied Physics Letters 95 (20), 202109, 2009
1152009
A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied toand InP Capacitors
G Brammertz, A Alian, DHC Lin, M Meuris, M Caymax, WE Wang
IEEE Transactions on Electron Devices 58 (11), 3890-3897, 2011
1082011
Capacitance-voltage characterization of interfaces
G Brammertz, HC Lin, K Martens, D Mercier, S Sioncke, A Delabie, ...
Applied Physics Letters 93 (18), 183504, 2008
1082008
The Fermi-level efficiency method and its applications on high interface trap density oxide-semiconductor interfaces
HC Lin, G Brammertz, K Martens, G de Valicourt, L Negre, WE Wang, ...
Applied physics letters 94 (15), 153508, 2009
772009
Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited as gate dielectric
HC Lin, T Yang, H Sharifi, SK Kim, Y Xuan, T Shen, S Mohammadi, PD Ye
Applied Physics Letters 91 (21), 212101, 2007
722007
Border traps in Ge/III–V channel devices: Analysis and reliability aspects
E Simoen, DHC Lin, A Alian, G Brammertz, C Merckling, J Mitard, ...
IEEE Transactions on Device and Materials Reliability 13 (4), 444-455, 2013
712013
Electrical properties of III-V/oxide interfaces
G Brammertz, HC Lin, K Martens, AR Alian, C Merckling, J Penaud, ...
ECS transactions 19 (5), 375, 2009
712009
Enabling the high-performance InGaAs/Ge CMOS: A common gate stack solution
D Lin, G Brammertz, S Sioncke, C Fleischmann, A Delabie, K Martens, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
682009
Advancing CMOS beyond the Si roadmap with Ge and III/V devices
M Heyns, A Alian, G Brammertz, M Caymax, YC Chang, LK Chu, ...
2011 International Electron Devices Meeting, 13.1. 1-13.1. 4, 2011
652011
Interfaces of high-k dielectrics on GaAs: Their common features and the relationship with Fermi level pinning
M Caymax, G Brammertz, A Delabie, S Sioncke, D Lin, M Scarrozza, ...
Microelectronic engineering 86 (7-9), 1529-1535, 2009
642009
Polarity control in WSe 2 double-gate transistors
GV Resta, S Sutar, Y Balaji, D Lin, P Raghavan, I Radu, F Catthoor, ...
Scientific reports 6 (1), 1-6, 2016
592016
Suitability of high-k gate oxides for III–V devices: A PBTI study in In0.53Ga0.47As devices with Al2O3
J Franco, A Alian, B Kaczer, D Lin, T Ivanov, A Pourghaderi, K Martens, ...
2014 IEEE International Reliability Physics Symposium, 6A. 2.1-6A. 2.6, 2014
582014
Bifunctional non-1397 noble metal oxide nanoparticle electrocatalysts through lithium-induced conversion for 1398 overall water splitting
H Wang, HW Lee, Y Deng, Z Lu, PC Hsu, Y Liu, D Lin, Y Cui
Nat. Comm 6, 1-8, 2015
572015
Doping-free complementary logic gates enabled by two-dimensional polarity-controllable transistors
GV Resta, Y Balaji, D Lin, IP Radu, F Catthoor, PE Gaillardon, ...
ACS nano 12 (7), 7039-7047, 2018
562018
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