| Field effect transistors having multiple stacked channels S Kim, D Park, CS Lee, JD Choe, SA Lee, SH Kim US Patent 7,002,207, 2006 | 214 | 2006 |
| Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors K Yeo, D Park, JD Choe US Patent 7,670,912, 2010 | 169 | 2010 |
| A novel multi-channel field effect transistor (McFET) on bulk Si for high performance sub-80nm application SM Kim, EJ Yoon, HJ Jo, M Li, CW Oh, SY Lee, KH Yeo, MS Kim, SH Kim, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 108 | 2004 |
| Methods of forming multi fin FETs using sacrificial fins and devices so formed S Kim, CS Lee, JD Choe, HJ Cho, EJ Yun, SA Lee US Patent App. 10/947,505, 2005 | 93 | 2005 |
| Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same CW Oh, D Park, S Lee, JD Choe, D Kim US Patent App. 11/065,002, 2005 | 85* | 2005 |
| Methods of fabricating field effect transistors having multiple stacked channels S Kim, D Park, CS Lee, JD Choe, SA Lee, SH Kim US Patent 7,381,601, 2008 | 78 | 2008 |
| Field effect transistors having multiple stacked channels S Kim, D Park, CS Lee, JD Choe, SA Lee, SH Kim US Patent 7,026,688, 2006 | 77 | 2006 |
| Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs) TS Park, HJ Cho, JD Choe, SY Han, D Park, K Kim, E Yoon, JH Lee IEEE Transactions on Electron Devices 53 (3), 481-487, 2006 | 69 | 2006 |
| Semiconductor devices with enlarged recessed gate electrodes SH Kim, CS Lee, JD Choe, S Kim, SA Lee, D Park US Patent 7,148,527, 2006 | 61 | 2006 |
| Stacked integrated circuit device including multiple substrates and method of manufacturing the same CW Oh, D Park, S Lee, JD Choe US Patent App. 10/977,702, 2005 | 49 | 2005 |
| Methods of fabricating field effect transistors having multiple stacked channels S Kim, D Park, CS Lee, JD Choe, SA Lee, SH Kim US Patent 7,615,429, 2009 | 42 | 2009 |
| Synchronous pulse plasma operation upon source and bias radio frequencys for inductively coupled plasma for highly reliable gate etching technology K Tokashiki, H Cho, S Banna, JY Lee, K Shin, V Todorow, WS Kim, ... Japanese journal of applied physics 48 (8S1), 08HD01, 2009 | 41 | 2009 |
| Semiconductor device having two different operation modes employing an asymmetrical buried insulating layer and method for fabricating the same CW Oh, D Park, S Lee, JD Choe US Patent 7,214,987, 2007 | 40 | 2007 |
| Fin field effect transistors and methods of fabricating the same C Lee, MS Kim, D Park, C Lee, CW Oh, JM Yoon, D Kim, JD Choe, M Li, ... US Patent App. 11/084,922, 2005 | 39 | 2005 |
| Methods of fabricating fin field transistors C Lee, MS Kim, D Park, C Lee, CW Oh, JM Yoon, D Kim, JD Choe, M Li, ... US Patent 7,332,386, 2008 | 38 | 2008 |
| A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors KH Yeo, CW Oh, SM Kim, MS Kim, CS Lee, SY Lee, SY Han, EJ Yoon, ... IEEE Electron Device Letters 25 (6), 387-389, 2004 | 37 | 2004 |
| Self-aligned semiconductor contact structures and methods for fabricating the same SH Kim, D Park, CS Lee, JD Choe, S Kim, SA Lee US Patent 7,071,517, 2006 | 35 | 2006 |
| Methods of forming field effect transistors including raised source/drain regions CW Oh, D Park, JD Choe, CS Lee US Patent 6,951,785, 2005 | 33 | 2005 |
| Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process YK Lee, KW Song, JW Hyun, JD Lee, BG Park, ST Kang, JD Choe, ... IEEE Electron Device Letters 25 (5), 317-319, 2004 | 32 | 2004 |
| Metal oxide semiconductor field effect transistors (MOSFETs) including recessed channel regions and methods of fabricating the same CW Oh, D Park, S Lee, CS Lee, JD Choe US Patent App. 10/795,653, 2004 | 31 | 2004 |
