| 33.4 A 28nm 2Mb STT-MRAM computing-in-memory macro with a refined bit-cell and 22.4-41.5 TOPS/W for AI inference H Cai, Z Bian, Y Hou, Y Zhou, Y Guo, X Tian, B Liu, X Si, Z Wang, J Yang, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 500-502, 2023 | 19 | 2023 |
| Cryogenic in-MRAM computing Y Hou, W Ge, Y Guo, L Naviner, Y Wang, B Liu, J Yang, H Cai 2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 1-6, 2021 | 2 | 2021 |
| A Sub-100nA Ultra-low Leakage MCU Embedding Always-on Domain Hybrid Tunnel FET-CMOS on 300mm Foundry Platform Y Hou, K Wang, C Liu-Sun, J Hang, X Tong, C Peng, Y Wu, Y Ren, W Bu, ... 2023 International Electron Devices Meeting (IEDM), 1-4, 2023 | 1 | 2023 |
| Dependable STT-MRAM with emerging approximation and speculation paradigms H Cai, Y Hou, M Zhang, B Liu, LA de Barros Naviner IEEE Design & Test 40 (3), 17-25, 2021 | 1 | 2021 |
| BIST-Supported Cryogenic Write Trimming With In-MRAM Computing Case Study Y Hou, C Liu-Sun, B Liu, H Zhang, H Cai IEEE Transactions on Nanotechnology 22, 126-135, 2023 | | 2023 |
Hao CaiSoutheast University, Nanjing, ChinaVerified email at telecom-paristech.fr
