Andre Reis
Andre Reis
Institute of Informatics - UFRGS
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Open Cell Library in 15nm FreePDK Technology
M Martins, JM Matos, RP Ribas, A Reis, G Schlinker, L Rech, J Michelsen
Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015
Boolean factoring with multi-objective goals
MGA Martins, L Rosa Jr, AB Rasmussen, RP Ribas, A Reis
Computer Design (ICCD), 2010 IEEE International Conference on, 229-234, 2010
Classifying n-input Boolean functions
VP Correia, AI Reis
VII Workshop Iberchip, 58, 2001
DAG based library-free technology mapping
FS Marques, LS Rosa Jr, RP Ribas, SS Sapatnekar, AI Reis
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 293-298, 2007
BTI, HCI and TDDB aging impact in flip–flops
C Nunes, PF Butzen, AI Reis, RP Ribas
Microelectronics Reliability 53 (9-11), 1355-1359, 2013
KL-cuts: a new approach for logic synthesis targeting multiple output blocks
O Martinello, FS Marques, RP Ribas, AI Reis
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 …, 2010
Exploring the use of approximate TMR to mask transient faults in logic with low area overhead
IAC Gomes, MGA Martins, AI Reis, FL Kastensmidt
Microelectronics Reliability 55 (9-10), 2072-2076, 2015
Exact lower bound for the number of switches in series to implement a combinational logic cell
FR Schneider, RP Ribas, SS Sapatnekar, AI Reis
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005 …, 2005
Associating CMOS transistors with BDD arcs for technology mapping
A Reis, M Robert, D Auvergne, R Reis
Electronics Letters 31 (14), 1118-1120, 1995
Advanced technology mapping for standard-cell generators
V Correia, A Reis
Proceedings of the 17th symposium on Integrated circuits and system design …, 2004
Power consumption analysis in static cmos gates
A Wiltgen, KA Escobar, AI Reis, RP Ribas
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
Library free technology mapping
AI Reis, R Reis, D Auvergne, M Robert
VLSI: Integrated Systems on Silicon, 303-314, 1997
Graph-based transistor network generation method for supergate design
VN Possani, V Callegaro, AI Reis, RP Ribas, F de Souza Marques, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 692-705, 2015
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
M Moreira, N Calazans, A Silva, M Martins, A Reis, R Ribas
International Symposium on Asynchronous Circuits and Systems (ASYNC), Potsdam, 2014
Switch level optimization of digital CMOS gate networks
LS da Rosa, FR Schneider, RP Ribas, AI Reis
2009 10th International Symposium on Quality Electronic Design, 324-329, 2009
Unified theory to build cell-level transistor networks from BDDs [logic synthesis]
REB Poli, FR Schneider, RP Ribas, AI Reis
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003
Covering strategies for library free technology mapping
AI Reis
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat …, 1999
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits
PF Butzen, LS da Rosa Jr, EJD Chiappetta Filho, AI Reis, RP Ribas
Microelectronics Journal 41 (4), 247-255, 2010
Synthesis of threshold logic gates to nanoelectronics
A Neutzling, MGA Martins, RP Ribas, AI Reis
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
Functional composition: A new paradigm for performing logic synthesis
MGA Martins, RP Ribas, AI Reis
Quality Electronic Design (ISQED), 2012 13th International Symposium on, 236-242, 2012
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