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Bin Li
Bin Li
Verified email at intel.com
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Year
ORION 2.0: A fast and accurate noc power and area model for early-stage design space exploration
K Samadi, A Kahng, B Li, L Peh
GSRC Annual Symposium 8, 2008
1004*2008
Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration
AB Kahng, B Li, LS Peh, K Samadi
Proceedings of the conference on Design, Automation and Test in Europe, 423-428, 2009
10032009
ORION 2.0: A Power-Area Simulator for Interconnection Networks
AB Kahng, B Li, LS Peh, K Samadi
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 1-5, 2012
3122012
CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs
B Li, L Zhao, R Iyer, LS Peh, M Leddige, M Espig, SE Lee, D Newell
Journal of Parallel and Distributed Computing 71 (5), 700-713, 2011
1332011
Impact of process and temperature variations on network-on-chip design exploration
B Li, LS Peh, P Patra
Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium …, 2008
872008
Polaris: A system-level roadmap for on-chip interconnection networks
V Soteriou, N Eisley, H Wang, B Li, LS Peh
Computer Design, 2006. ICCD 2006. International Conference on, 134-141, 2007
85*2007
A case study on the communication and computation behaviors of real applications in NoC-based MPSoCs
Z Wang, W Liu, J Xu, B Li, R Iyer, R Illikkal, X Wu, WH Mow, W Ye
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on, 480-485, 2014
402014
Polaris: A system-level roadmapping toolchain for on-chip interconnection networks
V Soteriou, N Eisley, H Wang, B Li, LS Peh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (8), 855-868, 2007
272007
Dynamic QoS management for chip multiprocessors
B Li, LS Peh, L Zhao, R Iyer
ACM Transactions on Architecture and Code Optimization 9, 17:1--17:29, 2012
212012
RAMBO: Resource Allocation for Microservices Using Bayesian Optimization
Q Li, B Li, P Mercati, R Illikkal, C Tai, M Kishinevsky, C Kozyrakis
IEEE Computer Architecture Letters 20 (1), 46-49, 2021
92021
RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization
B Li, Y Wang, R Wang, C Tai, R Iyer, Z Zhou, A Herdrich, T Zhang, ...
2020 6th IEEE Conference on Network Softwarization (NetSoft), 335-343, 2020
92020
Template-based memory access engine for accelerators in SoCs
B Li, Z Fang, R Iyer
Proceedings of the 16th Asia and South Pacific Design Automation Conference …, 2011
82011
Efficient peer-to-peer communication support in soc fabrics
B Li, L Zhao, R Iyer, RG Illikkal
US Patent App. 13/810,033, 2012
7*2012
A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems
W Liu, Z Wang, P Yang, J Xu, B Li, R Lyer, R Illikkal
IEEE Transactions on Multi-Scale Computing Systems 4 (2), 113-126, 2017
62017
Cache monitoring
R Wang, B Li, AJ Herdrich, TC Tai, R Huggahalli
US Patent 10,599,548, 2020
52020
A systematic network-on-chip traffic modeling and generation methodology
Z Wang, W Liu, J Xu, X Wu, Z Wang, B Li, R Iyer, R Illikkal
Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on, 675-678, 2014
52014
Cost-effectively offering private buffers in SoCs and CMPs
Z Fang, L Zhao, RR Iyer, CF Fajardo, GF Garcia, SE Lee, B Li, SR King, ...
Proceedings of the international conference on Supercomputing, 275-284, 2011
42011
Boomerang: reducing power consumption of response packets in NoCs with minimal performance impact
Z Fang, E Hallnor, B Li, M Leddige, D Dai, SE Lee, S Makineni, R Iyer
IEEE Computer Architecture Letters 9 (2), 49-52, 2010
42010
PROMPT: Learning Dynamic Resource Allocation Policies for Edge-Network Applications
D Penney, B Li, J Sydir, C Tai, E Walsh, T Long, S Lee, L Chen
arXiv preprint arXiv:2201.07916, 2022
2022
Apparatus and method for a closed-loop dynamic resource allocation control framework
B Li, R Wang, KA Doshi, FG Bernat, Y Wang, R Iyer, A Herdrich, TY Tai, ...
US Patent App. 16/914,305, 2021
2021
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