| An optimization based approach to the partial scan design problem V Chickermane, JH Patel Proceedings. International Test Conference 1990, 377-386, 1990 | 191 | 1990 |
| A fault oriented partial scan design approach V Chickermane, JH Patel 1991 IEEE International Conference on Computer-Aided Design Digest of …, 1991 | 155 | 1991 |
| Channel masking synthesis for efficient on-chip test compression V Chickermane, B Foutz, B Keller 2004 International Conferce on Test, 452-461, 2004 | 143 | 2004 |
| Non-scan design-for-testability techniques for sequential circuits V Chickermane, EM Rudnick, P Banerjee, JH Patel Proceedings of the 30th international Design Automation Conference, 236-241, 1993 | 69 | 1993 |
| Addressing design for testability at the architectural level V Chickermane, J Lee, JH Patel IEEE transactions on computer-aided design of integrated circuits and …, 1994 | 49 | 1994 |
| Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study SK Goel, S Adham, MJ Wang, JJ Chen, TC Huang, A Mehta, F Lee, ... 2013 IEEE International Test Conference (ITC), 1-10, 2013 | 44 | 2013 |
| Capture power reduction using clock gating aware test generation K Chakravadhanula, V Chickermane, B Keller, P Gallagher, P Narang 2009 International Test Conference, 1-9, 2009 | 40 | 2009 |
| Distributed test compression for integrated circuits B Foutz, P Gallagher, V Chickermane, C Barnhart US Patent 7,979,764, 2011 | 37 | 2011 |
| Design for testability using architectural descriptions V Chickermane, J Lee, JH Patel Proceedings International Test Conference 1992, 752-752, 1992 | 34 | 1992 |
| A building block BIST methodology for SOC designs: A case study P Gallagher, V Chickermane, S Gregor, TS Pierre Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 111-120, 2001 | 33 | 2001 |
| An economic analysis and ROI model for nanometer test B Keller, M Tegethoff, T Bartenstein, V Chickermane 2004 International Conferce on Test, 518-524, 2004 | 32 | 2004 |
| An observability enhancement approach for improved testability and at-speed test EM Rudnick, V Chickermane, JH Patel IEEE transactions on computer-aided design of integrated circuits and …, 1994 | 30 | 1994 |
| Automation of 3D-DfT insertion S Deutsch, V Chickermane, B Keller, S Mukherjee, M Konijnenburg, ... 2011 Asian Test Symposium, 395-400, 2011 | 29 | 2011 |
| A comparative study of design for testability methods using high-level and gate-level descriptions Chickermane, Lee, Patel 1992 IEEE/ACM International Conference on Computer-Aided Design, 620-624, 1992 | 27 | 1992 |
| A power-aware test methodology for multi-supply multi-voltage designs V Chickermane, P Gallagher, J Sage, P Yuan, K Chakravadhanula 2008 IEEE International Test Conference, 1-10, 2008 | 26 | 2008 |
| Advancing test compression to the physical dimension K Chakravadhanula, V Chickermane, P Cunningham, B Foutz, D Meehl, ... 2017 IEEE International Test Conference (ITC), 1-10, 2017 | 24 | 2017 |
| SmartScan-Hierarchical test compression for pin-limited low power designs K Chakravadhanula, V Chickermane, D Pearl, A Garg, R Khurana, ... 2013 IEEE International Test Conference (ITC), 1-9, 2013 | 22 | 2013 |
| At-speed testing of inter-die connections of 3D-SICs in the presence of shore logic K Shibin, V Chickermane, B Keller, C Papameletis, EJ Marinissen 2015 IEEE 24th Asian Test Symposium (ATS), 79-84, 2015 | 20 | 2015 |
| Testing state retention logic in low power systems K Chakravadhanula, P Gallagher, V Chickermane, SL Gregor, P Arora US Patent 8,271,226, 2012 | 19 | 2012 |
| Method and apparatus for low-pin count testing of integrated circuits K Chakravadhanula, V Chickermane, D Meehl US Patent 8,650,524, 2014 | 18 | 2014 |
