| On Testing of Superscalar Processors in Functional Mode for Delay Faults N Hage, R Gulve, M Fujita, V Singh VLSI Design and 2017 16th International Conference on Embedded Systems …, 2017 | 14 | 2017 |
| A low cost technique for scan chain diagnosis S Ahlawat, D Vaghani, R Gulve, V Singh Circuits and Systems (ISCAS), 2017 IEEE International Symposium on, 1-4, 2017 | 7 | 2017 |
| ILP based don R Gulve, V Singh 2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016 | 6 | 2016 |
| Instruction-based self-test for delay faults maximizing operating temperature N Hage, R Gulve, M Fujita, V Singh On-Line Testing and Robust System Design (IOLTS), 2017 IEEE 23rd …, 2017 | 4 | 2017 |
| On determination of instantaneous peak and cycle peak switching using ILP R Gulve, N Hage, J Tudu VLSI Design and Test (VDAT), 2016 20th International Symposium on, 1-6, 2016 | 4 | 2016 |
| PHP: Power hungry pattern generation at higher abstraction level R Gulve, A Goel, V Singh East-West Design & Test Symposium (EWDTS), 2017 IEEE, 1-4, 2017 | 3 | 2017 |
| ATPG power guards: On limiting the test power below threshold R Gulve, V Singh Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018 …, 2018 | 1 | 2018 |
| Multi-mode Toggle Random Access Scan to Minimize Test Application Time A Goel, R Gulve International Symposium on VLSI Design and Test, 205-216, 2017 | | 2017 |
| On Generation of Delay Test with Capture Power Safety R Gulve, N Hage International Symposium on VLSI Design and Test, 607-618, 2017 | | 2017 |
| Enabling LOS delay test with slow scan enable S Ahlawat, D Vaghani, R Gulve, V Singh 2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016 | | 2016 |
Virendra SinghAssociate Professor of Electrical Engineering, Indian Institute of Technology BombayAdresse e-mail validée de ee.iitb.ac.in
