Somayeh Timarchi
Somayeh Timarchi
Assistant Professor, Department of Electronics, Shahid Beheshti University G. C., Tehran, Iran
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Efficient Reverse Converter Designs for the New 4-Moduli Sets and Based on New CRTs
AS Molahosseini, K Navi, C Dadkhah, O Kavehei, S Timarchi
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (4), 823-835, 2009
A novel low-power full-adder cell for low voltage
K Navi, M Maeen, V Foroutan, S Timarchi, O Kavehei
Integration 42 (4), 457-467, 2009
Arithmetic circuits of redundant SUT-RNS
S Timarchi, K Navi
IEEE Transactions on instrumentation and measurement 58 (9), 2959-2968, 2009
Low-power and fast full adder by exploring new XOR and XNOR gates
H Naseri, S Timarchi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (8 …, 2018
An ultra-low-power 9T SRAM cell based on threshold voltage techniques
M Moghaddam, S Timarchi, MH Moaiyeri, M Eshghi
Circuits, Systems, and Signal Processing 35 (5), 1437-1455, 2016
New Design of RNS Subtractor for modulo 2n+ 1
S Timarchi, K Navi, M Hosseinzade
2006 2nd International Conference on Information & Communication …, 2006
Improved modulo 2n+ 1 adder design
S Timarchi, K Navi
International Journal of Computer and Information Engineering 2 (7), 443-450, 2008
Efficient class of redundant residue number system
S Timarchi, K Navi
2007 IEEE International Symposium on Intelligent Signal Processing, 1-6, 2007
A novel high-speed low-power binary signed-digit adder
S Timarchi, P Ghayour, A Shahbahrami
The 16th CSI International Symposium on Computer Architecture and Digital …, 2012
A unified addition structure for moduli set {2n−1, 2n, 2n+1} based on a novel RNS representation
S Timarchi, M Fazlali, SD Cotofana
2010 IEEE International Conference on Computer Design, 247-252, 2010
Maximally redundant high-radix signed-digit adder: new algorithm and implementation
S Timarchi, K Navi, O Kavehei
2009 IEEE Computer Society Annual Symposium on VLSI, 97-102, 2009
Low power modulo 2 n+ 1 adder based on carry save diminished-one number system
S Timarchi, O Kavehei, K Navi
American Journal of Applied Sciences 5 (4), 312-319, 2008
Design of Residue Number System Circuits in Current mode
M Hosseinzadeh, K Navi, S Timarchi
Proc. 14th Iranian Conference of Electrical Engineering, 2006
New Design of 4-3 Compressor
M Hosseinzadeh, K Navi, S Timarchi
Proc. 11th International CSI Computer Conference of Iran, 2006
High-speed energy-efficient 5: 2 compressor
A Najafi, S Timarchi, A Najafi
2014 37th International Convention on Information and Communication …, 2014
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n− 1, 2n, 2n+ 1}
S Timarchi, M Fazlali
IET computers & digital techniques 6 (5), 269-276, 2012
Efficient reverse converter designs for the new 4-moduli sets {2n–1, 2n, 2n+ 1, 22n+ 1–1} and {2n–1, 2n+ 1, 22n, 22n+ 1} based on new CRTs
A Sabbagh, K Navi, C Dadkhah, O Kavehei, S Timarchi
IEEE Trans. Circuit and Systems I 57 (4), 2010
Low power design of binary signed digit residue number system adder
A Armand, S Timarchi
2016 24th Iranian Conference on Electrical Engineering (ICEE), 844-848, 2016
High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding
S Timarchi, M Saremi, M Fazlali, G Gaydadjiev
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013
Low-power DCT-based compressor for wireless capsule endoscopy
A Shabani, S Timarchi
Signal Processing: Image Communication 59, 83-95, 2017
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