| Theoretical aspects of Petri nets decomposition based on invariants and hypergraphs R Wiśniewski, Ł Stefanowicz, A Bukowiec, J Lipiński Multimedia and ubiquitous engineering, 371-376, 2014 | 25 | 2014 |
| Benefits of Hardware Accelerated Simulation R Wiśniewski, A Bukowiec, M Węgrzyn Discrete-Event System Design (DESDes), 2001 Proceedings of the International …, 2001 | 25 | 2001 |
| Synthesis of Finite State Machines for FPGA Devices Based on Architectural Decomposition A Bukowiec University of Zielona Góra Press 13 (Lecture Notes in Control and Computer …, 2009 | 23 | 2009 |
| Synthesis of Petri nets into FPGA with operation flexible memories A Bukowiec, M Adamski 2012 IEEE 15th International Symposium on Design and Diagnostics of …, 2012 | 21 | 2012 |
| Petri Net Dynamic Partial Reconfiguration in FPGA A Bukowiec, M Doligalski Computer Aided Systems Theory-EUROCAST 2013, 436-443, 2013 | 19 | 2013 |
| UML modelling in rigorous design methodology for discrete controllers G Łabiak, M Adamski, M Doligalski, J Tkacz, A Bukowiec International Journal of Electronics and Telecommunications 58 (1), 27-34, 2012 | 18 | 2012 |
| Synthesis of finite state machines for programmable devices based on multi-level implementation A Bukowiec Ph.D. thesis, University of Zielona Gora, Poland, 2008 | 13 | 2008 |
| Synthesis of FSMs based on architectural decomposition with joined multiple encoding A Bukowiec International Journal of Electronics and Telecommunications 58 (1), 35-41, 2012 | 12 | 2012 |
| An FPGA Synthesis of the Distributed Control Systems Designed with Petri Nets A Bukowiec, P Mróz Networked Embedded Systems for Every Application (NESEA), 2012 3rd IEEE …, 2012 | 11 | 2012 |
| Synthesis of macro Petri nets into FPGA with distributed memories A Bukowiec, M Adamski International Journal of Electronics and Telecommunications 58 (4), 403-410, 2012 | 11 | 2012 |
| Efficient logic controller design G Borowik, M Rawski, G Łabiak, A Bukowiec, H Selvaraj 2010 Fifth International Conference on Broadband and Biomedical …, 2010 | 11 | 2010 |
| Synthesis of Mealy finite states machines for interpretation of verticalized flow-charts A Barkalov, A Bukowiec Informatyka Teoretyczna i Stosowana 5 (8), 39-51, 2005 | 11 | 2005 |
| Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA A Bukowiec, J Tkacz, T Gratkowski, T Gidlewicz International Journal of Electronics and Telecommunications 59 (4), 317-324, 2013 | 10 | 2013 |
| Partial reconfiguration in the field of logic controllers design M Doligalski, A Bukowiec International Journal of Electronics and Telecommunications 59 (4), 351-356, 2013 | 8 | 2013 |
| Structural decomposition of finite state machines A Bukowiec, A Barkalov Electronics and Telecommunications Quarterly 55 (2), 243-267, 2009 | 8 | 2009 |
| Design of Reconfigurable Logic Controllers A Karatkevich, A Bukowiec, M Doligalski, J Tkacz Springer International Publishing, 2016 | 7 | 2016 |
| FSM-based logic controller synthesis in programmable devices with embedded memory blocks G Borowik, G Łabiak, A Bukowiec Innovative Technologies in Management and Science, 123-151, 2015 | 6 | 2015 |
| Synthesis of Mealy FSM with multiple shared encoding of microinstructions and internal states A Bukowiec Programmable Devices and Embedded Systems (PDeS), 2006 Proceedings of IFAC …, 2006 | 6 | 2006 |
| Logic synthesis for FPGAs of interpreted Petri net with common operation memory A Bukowiec, M Adamski IFAC Proceedings Volumes 45 (7), 57-62, 2012 | 5 | 2012 |
| Automata Synthesis System A Bukowiec | 5 | 2008 |
Alexander BarkalovProfessor, University of Zielona GóraAdresse e-mail validée de iie.uz.zgora.pl
