Jean-Luc Danger
Jean-Luc Danger
LTCI, Télécom Paris, Institut Polytechnique de Paris
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Practical setup time violation attacks on AES
N Selmane, S Guilley, JL Danger
2008 Seventh European Dependable Computing Conference, 91-96, 2008
λ-min decoding algorithm of regular and irregular LDPC codes
F Guilloud, E Boutillon, JL Danger
Proceedings of the 3rd international symposium on turbo codes and related …, 2003
RSM: a small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs
M Nassar, Y Souissi, S Guilley, JL Danger
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
High speed true random number generator based on open loop structures in FPGAs
JL Danger, S Guilley, P Hoogvorst
Microelectronics journal 40 (11), 1650-1656, 2009
Hardware Trojan horses in cryptographic IP cores
S Bhasin, JL Danger, S Guilley, XT Ngo, L Sauvage
2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 15-29, 2013
Efficient FPGA implementation of Gaussian noise generator for communication channel emulation
JL Danger, A Ghazel, E Boutillon, H Laamari
ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and …, 2000
BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation
M Nassar, S Bhasin, JL Danger, G Duc, S Guilley
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Design of high speed AWGN communication channel emulator
E Boutillon, JL Danger, A Ghazel
Analog Integrated Circuits and Signal Processing 34 (2), 133-142, 2003
Design and performance analysis of a high speed AWGN communication channel emulator
A Ghazel, E Boutillon, JL Danger, G Gulak, H Laamari
2001 IEEE Pacific Rim Conference on Communications, Computers and Signal …, 2001
Generic description and synthesis of LDPC decoders
F Guilloud, E Boutillon, J Tousch, JL Danger
IEEE transactions on Communications 55 (11), 2084-2091, 2007
WDDL is protected against setup time violation attacks
N Selmane, S Bhasin, S Guilley, T Graba, JL Danger
2009 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 73-83, 2009
NICV: normalized inter-class variance for detection of side-channel leakage
S Bhasin, JL Danger, S Guilley, Z Najm
2014 International Symposium on Electromagnetic Compatibility, Tokyo, 310-313, 2014
High precision fault injections on the instruction cache of ARMv7-M architectures
L Riviere, Z Najm, P Rauzy, JL Danger, J Bringer, L Sauvage
2015 IEEE International Symposium on Hardware Oriented Security and Trust …, 2015
Analysis of electromagnetic information leakage from cryptographic devices with different physical structures
YI Hayashi, N Homma, T Mizuki, T Aoki, H Sone, L Sauvage, JL Danger
IEEE Transactions on Electromagnetic Compatibility 55 (3), 571-580, 2012
An easy-to-design PUF based on a single oscillator: the loop PUF
Z Cherif, JL Danger, S Guilley, L Bossuet
2012 15th Euromicro Conference on Digital System Design, 156-162, 2012
Digital delay line
JL Danger
US Patent 5,719,515, 1998
Software implementation of dual-rail representation
P Hoogvorst, G Duc, JL Danger
COSADE, February, 24-25, 2011
Random active shield
S Briais, JM Cioranesco, JL Danger, S Guilley, D Naccache, T Porteboeuf
2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 103-113, 2012
Overview of dual rail with precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors
JL Danger, S Guilley, S Bhasin, M Nassar
2009 3rd International Conference on Signals, Circuits and Systems (SCS), 1-8, 2009
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
L Sauvage, S Guilley, JL Danger, Y Mathieu, M Nassar
2009 Design, Automation & Test in Europe Conference & Exhibition, 640-645, 2009
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