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Pascal Sainrat
Pascal Sainrat
Professor in Computer Science, Traces-IRIT, Université Paul Sabatier - Toulouse III
Verified email at irit.fr - Homepage
Title
Cited by
Cited by
Year
OTAWA: An open toolbox for adaptive WCET analysis
C Ballabriga, H Cassé, C Rochange, P Sainrat
Software Technologies for Embedded and Ubiquitous Systems: 8th IFIP WG 10.2 …, 2010
2722010
Merasa: Multicore execution of hard real-time applications supporting analyzability
T Ungerer, F Cazorla, P Sainrat, G Bernat, Z Petrov, C Rochange, ...
IEEE Micro 30 (5), 66-75, 2010
2232010
Papabench: a free real-time benchmark
F Nemer, H Cassé, P Sainrat, JP Bahsoun, M De Michiel
6th International Workshop on Worst-Case Execution Time Analysis (WCET'06), 2006
1892006
Multiple-block ahead branch predictors
A Seznec, S Jourdan, P Sainrat, P Michaud
ACM SIGPLAN Notices 31 (9), 116-127, 1996
1551996
Multiple-mode memory component
D Litaize, JC Salinier, A Mzoughi, FZ Elkhlifi, M Lalam, P Sainrat
US Patent 6,345,321, 2002
1102002
Static loop bound analysis of C programs based on flow analysis and abstract interpretation
M De Michiel, A Bonenfant, H Cassé, P Sainrat
2008 14th IEEE International Conference on Embedded and Real-Time Computing …, 2008
842008
parMERASA--multi-core execution of parallelised hard real-time applications supporting analysability
T Ungerer, C Bradatsch, M Gerdes, F Kluge, R Jahr, J Mische, ...
2013 Euromicro Conference on Digital System Design, 363-370, 2013
802013
High-performance embedded architecture and compilation roadmap
K De Bosschere, W Luk, X Martorell, N Navarro, M O'Boyle, ...
Trans. High Perform. Embed. Archit. Compil. 1, 5-29, 2007
762007
OTAWA, a framework for experimenting WCET computations
H Cassé, P Sainrat
Conference ERTS'06, 2006
652006
A context-parameterized model for static analysis of execution times
C Rochange, P Sainrat
Transactions on High-Performance Embedded Architectures and Compilers II …, 2009
622009
Automatic WCET analysis of real-time parallel applications
H Ozaktas, C Rochange, P Sainrat
13th International Workshop on Worst-Case Execution Time Analysis, 2013
612013
Multiple-mode memory system
D Litaize, JC Salinier, A Mzoughi, FZ Elkhlifi, M Lalama, P Sainrat
US Patent App. 10/212,682, 2003
612003
Exploring configurations of functional units in an out-of-order superscalar processor
S Jourdan, P Sainrat, D Litaize
Proceedings of the 22nd annual international symposium on Computer …, 1995
601995
Mapping hard real-time applications on many-core processors
Q Perret, P Maurère, É Noulard, C Pagetti, P Sainrat, B Triquet
Proceedings of the 24th International Conference on Real-Time Networks and …, 2016
532016
WCET analysis of a parallel 3D multigrid solver executed on the MERASA multi-core
C Rochange, A Bonenfant, P Sainrat, M Gerdes, J Wolf, T Ungerer, ...
10th International Workshop on Worst-Case Execution Time Analysis (WCET 2010), 2010
522010
Temporal isolation of hard real-time applications on many-core processors
Q Perret, P Maurere, E Noulard, C Pagetti, P Sainrat, B Triquet
2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2016
452016
Memory component with configurable multiple transfer formats
D Litaize, JC Salinier, A Mzoughi, FZ Elkhlifi, M Lalam, P Sainrat
US Patent 6,748,509, 2004
452004
Accurate analysis of memory latencies for WCET estimation
R Bourgade, C Ballabriga, H Cassé, C Rochange, P Sainrat
16th international conference on real-time and network systems (RTNS 2008), 2008
442008
Memory controller for synchronous burst transfers
D Litaize, JC Salinier, A Mzoughi, FZ Elkhlifi, M Lalam, P Sainrat
US Patent 7,136,971, 2006
432006
Time analysable synchronisation techniques for parallelised hard real-time applications
M Gerdes, F Kluge, T Ungerer, C Rochange, P Sainrat
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 671-676, 2012
402012
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