| A low-complexity high-speed clock generator for dynamic frequency scaling of fpga and standard-cell based designs B Pontikakis, HT Bui, FR Boyer, Y Savaria 2007 IEEE International Symposium on Circuits and Systems, 633-636, 2007 | 14 | 2007 |
| Precise free-running period synthesizer (FRPS) with process and temperature compensation B Pontikakis, FR Boyer, Y Savaria, HT Bui 2007 50th Midwest Symposium on Circuits and Systems, 1118-1121, 2007 | 9 | 2007 |
| A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications B Pontikakis, M Nekili 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat …, 2002 | 8 | 2002 |
| An all-digital skew-adaptive clock scheduling algorithm for heterogeneous multiprocessor systems on chips (MPSoCs) SR Hasan, B Pontikakis, Y Savaria 2009 IEEE International Symposium on Circuits and Systems, 2501-2504, 2009 | 7 | 2009 |
| A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications FR Boyer, HG Epassa, B Pontikakis, Y Savaria, W Ling The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS …, 2004 | 7 | 2004 |
| Performance improvement of configurable processor architectures using a variable clock period B Pontikakis, Y Savaria, FR Boyer Fifth International Workshop on System-on-Chip for Real-Time Applications …, 2005 | 5 | 2005 |
| A new area-power efficient split-output TSPC CMOS latch for high-speed VLSI applications B Pontikakis, M Nekili ICM 2001 Proceedings. The 13th International Conference on Microelectronics …, 2001 | 5 | 2001 |
| A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs B Pontikakis, HT Bui, FR Boyer, Y Savaria 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems …, 2008 | 3 | 2008 |
| A 0.8 V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs B Pontikakis, FR Boyer, Y Savaria 2006 IEEE International Symposium on Circuits and Systems, 4 pp.-1262, 2006 | 2 | 2006 |
| A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications B Pontikakis Concordia University, 2003 | 2 | 2003 |
| A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices M Elbediwy, B Pontikakis, JP David, Y Savaria IEEE Access, 2023 | 1 | 2023 |
| DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue M Elbediwy, B Pontikakis, A Ghaffari, JP David, Y Savaria IEEE Transactions on Network and Service Management, 2023 | | 2023 |
| An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices M Su, JP David, Y Savaria, B Pontikakis, T Luinaud 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2529-2533, 2022 | | 2022 |
Yvon SavariaProfesseur in Electrical Engineering, Polytechnique MontrealAdresse e-mail validée de polymtl.ca
