| AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications DH Bui, D Puschini, S Bacles-Min, E Beigné, XT Tran IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017 | 95 | 2017 |
| Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications DH Bui, D Puschini, S Bacles-Min, E Beigné, XT Tran 2016 International Conference on IC Design and Technology (ICICDT), 1-4, 2016 | 34 | 2016 |
| A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization ND Nguyen, DH Bui, XT Tran 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 33-36, 2019 | 22 | 2019 |
| An Efficient Hardware Implementation of Artificial Neural Network based on Stochastic Computing DA Nguyen, HH Ho, DH Bui, XT Tran 2018 5th NAFOSTED Conference on Information and Computer Science (NICS), 237-242, 2018 | 16 | 2018 |
| Hardware implementation for entropy coding and byte stream packing engine in H. 264/AVC NM Nguyen, E Beigne, S Lesecq, P Vivet, DH Bui, XT Tran 2013 International Conference on Advanced Technologies for Communications …, 2013 | 11 | 2013 |
| Efficient Binary Arithmetic Encoder for HEVC with multiple bypass bin processing QL Nguyen, DL Tran, DH Bui, DT Mai, XT Tran 2017 7th International Conference on Integrated Circuits, Design, and …, 2017 | 9 | 2017 |
| A Lightweight AEAD encryption core to secure IoT applications ND Nguyen, DH Bui, XT Tran 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 35-38, 2020 | 7 | 2020 |
| An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder DL Tran, XT Tran, DH Bui, CK Pham Electronics 9 (4), 684, 2020 | 7 | 2020 |
| High-performance adaption of ARM processors into Network-on-Chip architectures T Nguyen, DH Bui, HP Phan, TT Dang, XT Tran 2013 IEEE International SOC Conference, 222-227, 2013 | 7 | 2013 |
| H. 264/AVC hardware encoders and low-power features NM Nguyen, E Beigne, S Lesecq, DH Bui, NK Dang, XT Tran 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 77-80, 2014 | 6 | 2014 |
| A hardware architecture for intra prediction in H. 264/AVC encoder DH Bui, VH Tran, VM Nguyen, DH Ngo, XT Tran | 5 | 2012 |
| An innovative lightweight cryptography system for Internet-of-Things ULP applications DH Bui | 4 | 2019 |
| AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures XT Tran, T Nguyen, HP Phan, DH Bui IEICE Transactions on Fundamentals of Electronics, Communications and …, 2017 | 4 | 2017 |
| An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks DA Nguyen, DH Bui, F Iacopi, XT Tran 2019 32nd IEEE International System-on-Chip Conference (SOCC), 144-149, 2019 | 3 | 2019 |
| Accurate and low complex cell histogram generation by bypass the gradient of pixel computation HH Ho, NS Nguyen, DH Bui, XT Tran 2017 4th NAFOSTED Conference on Information and Computer Science, 201-206, 2017 | 3 | 2017 |
| Reducing temporal redundancy in MJPEG using Zipfian estimation techniques NS Nguyen, DH Bui, XT Tran 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 65-68, 2014 | 3 | 2014 |
| An Overview of H. 264 Hardware Encoder Architectures Including Low-Power Features NM Nguyen, DH Bui, NK Dang, E Beigne, S Lesecq, P Vivet, XT Tran REV Journal on Electronics and Communications 4 (1-2), 34-43, 2014 | 3 | 2014 |
| Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks XT Tran, NS Nguyen, DH Bui, MT Pham, H Nguyen, CK Pham EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 7 (22), 2020 | 2 | 2020 |
| Low Cost Inter-prediction Architecture in H. 264/AVC Encoders with an Efficient Data Reuse Strategy XT Tran, NK Dang, DH Bui, A Merigot Nova Science Publishers, 2021 | | 2021 |
| Thiết kế bộ khuếch đại công suất cao tần hiệu suất cao trên công nghệ CMOS 65nm cho các ứng dụng IoT tốc độ cao DM Tran, DH Bui, TTQ Tran, VTV Le, XT Tran | | 2020 |
