| Application-to-core mapping policies to reduce memory system interference in multi-core systems R Das, R Ausavarungnirun, O Mutlu, A Kumar, M Azimi 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 149 | 2013 |
| Integration Challenges and Tradeoffs for Tera-scale Architectures. M Azimi, N Cherukuri, DN Jayasimha, A Kumar, P Kundu, S Park, ... Intel Technology Journal 11 (3), 2007 | 130 | 2007 |
| Method and apparatus for reducing memory latency in a cache coherent multi-node architecture M Khare, FA Briggs, A Kumar, LP Looi, K Cheng US Patent 7,234,029, 2007 | 99* | 2007 |
| Method and apparatus for managing transaction requests in a multi-node architecture M Khare, A Kumar, I Schoinas, LP Looi US Patent 6,971,098, 2005 | 87 | 2005 |
| Mechanism for handling explicit writeback in a cache coherent multi-node architecture M Khare, LP Looi, A Kumar US Patent 6,842,830, 2005 | 87 | 2005 |
| Cascade lake: Next generation intel xeon scalable processor M Arafa, B Fahim, S Kottapalli, A Kumar, LP Looi, S Mandava, A Rudoff, ... IEEE Micro 39 (2), 29-36, 2019 | 84 | 2019 |
| Mechanism for efficiently supporting the full MESI (modified, exclusive, shared, invalid) protocol in a cache coherent multi-node shared memory system M Khare, L Looi, A Kumar, F Briggs US Patent App. 09/752,534, 2003 | 68 | 2003 |
| Mechanism for efficiently supporting the full MESI (modified, exclusive, shared, invalid) protocol in a cache coherent multi-node shared memory system M Khare, L Looi, A Kumar, F Briggs US Patent App. 09/752,534, 2003 | 68 | 2003 |
| Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture M Khare, LP Looi, A Kumar, FA Briggs US Patent 6,615,319, 2003 | 65 | 2003 |
| Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture M Khare, LP Looi, A Kumar, FA Briggs US Patent 6,615,319, 2003 | 65 | 2003 |
| Method and apparatus for preventing starvation in a multi-node architecture M Khare, A Kumar US Patent 6,487,643, 2002 | 52 | 2002 |
| Mechanism for handling explicit writeback in a cache coherent multi-node architecture M Khare, LP Looi, A Kumar US Patent 6,842,830, 2005 | 47 | 2005 |
| Conditional and vectored system management interrupts M Ayyar, I Schoinas, RR Menon, A Vaidya, A Kumar US Patent 7,433,985, 2008 | 35 | 2008 |
| Link level retry scheme CT Chou, S Chittor, A Khan, A Kumar, PK Mannava, RS Ram, S Sen, ... US Patent 7,016,304, 2006 | 35* | 2006 |
| Replacing cache lines in a cache memory based at least in part on cache coherency state information N Cherukuri, DW Brzezinski, IT Schoinas, A Shayesteh, A Kumar, M Azimi US Patent 8,990,506, 2015 | 32 | 2015 |
| Application-to-core mapping policies to reduce memory interference in multi-core systems R Das, R Ausavarungnirun, O Mutlu, A Kumar, M Azimi 2012 21st International Conference on Parallel Architectures and Compilation …, 2012 | 31 | 2012 |
| Optimizing concurrent accesses in a directory-based coherency protocol H Thantry, A Kumar, S Park US Patent 8,190,820, 2012 | 31 | 2012 |
| Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line M Khare, LP Looi, A Kumar, KC Creta US Patent 6,859,864, 2005 | 31 | 2005 |
| Evaluating virtual channels for cache-coherent shared-memory multiprocessors A Kumar, LN Bhuyan Proceedings of the 10th international conference on Supercomputing, 253-260, 1996 | 31 | 1996 |
| Modular decoupled crossbar for on-chip router D Park, A Vaidya, A Kumar, M Azimi US Patent 9,674,114, 2017 | 29 | 2017 |
