| Common Readout Unit (CRU)-A new readout architecture for the ALICE experiment RP J Mitra, SA Khan, S Mukherjee Journal of Instrumentation 11 (03), C03021, 2016 | 39 | 2016 |
| Fault Matters: Sensor Data Fusion for Detection of Faults using Dempster-Shafer Theory of Evidence in IoT-Based Applications N Ghosh, R Paul, S Maity, K Maity, S Saha Expert Systems with Applications 162, 2020 | 34 | 2020 |
| IoT based secure smart city architecture using blockchain R Paul, P Baidya, S Sau, K Maity, S Maity, SB Mandal 2018 2nd international conference on data science and business analytics …, 2018 | 32 | 2018 |
| Outlier detection in sensor data using machine learning techniques for IoT framework and wireless sensor networks: A brief study N Ghosh, K Maity, R Paul, S Maity 2019 International Conference on Applied Machine Learning (ICAML), 187-190, 2019 | 26 | 2019 |
| iDCR: Improved Dempster Combination Rule for Multisensor Fault Diagnosis RP Nimisha Ghosh, Sayantan Saha Engineering Applications of Artificial Intelligence 104, 369, 2021 | 15* | 2021 |
| Partitioned security processor architecture on FPGA platform R Paul, S Shukla IET Computers & Digital Techniques 12 (5), 216-226, 2018 | 15 | 2018 |
| Blockchain based secure smart city architecture using low resource IoTs R Paul, N Ghosh, S Sau, A Chakrabarti, P Mohapatra Computer Networks 196, 108234, 2021 | 12 | 2021 |
| HealthCare EHR: A Blockchain-Based Decentralized Application A Panigrahi, AK Nayak, R Paul International Journal of Information Systems and Supply Chain Management …, 2022 | 11 | 2022 |
| Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication R Paul, S Saha, S Sau, A Chakrabarti IEMCON2012, Kolkata, 2012 | 11 | 2012 |
| A novel method for soft error mitigation in FPGA using modified matrix code S Mandal, R Paul, S Sau, A Chakrabarti, S Chattopadhyay IEEE Embedded Systems Letters 8 (4), 65-68, 2016 | 10 | 2016 |
| Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm R Paul, A Chakrabarti, R Ghosh Microprocessors and Microsystems 40, 124-136, 2016 | 10 | 2016 |
| A simple 1-byte 1-clock RC4 hardware design and its implementation in FPGA coprocessor for secured Ethernet communication R Paul, S Saha, J Zaman, S Das, A Chakrabarti, R Ghosh Proc. National Workshop on Cryptology, VIT University & CRSI, Vellore, India, 2012 | 9* | 2012 |
| Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware S Mandal, R Paul, S Sau, A Chakrabarti, S Chattopadhyay Microprocessors and Microsystems 51, 313-330, 2017 | 8 | 2017 |
| Real time communication between multiple FPGA systems in multitasking environment using RTOS R Paul, S Saha, S Sau, A Chakrabarti 2012 International Conference on Devices, Circuits and Systems (ICDCS), 130-134, 2012 | 8 | 2012 |
| A novel AES-256 implementation on FPGA using co-processor based architecture S Sau, R Paul, T Biswas, A Chakrabarti Proceedings of the International Conference on Advances in Computing …, 2012 | 6 | 2012 |
| Novel architecture of modular exponent on reconfigurable system R Paul, S Saha, C Pal, S Sau 2012 Students Conference on Engineering and Systems, 1-6, 2012 | 6 | 2012 |
| Hardware implementation of four byte per clock RC4 algorithm R Paul, A Chakrabarti, R Ghosh arXiv preprint arXiv:1401.2727, 2014 | 5 | 2014 |
| Performance Evaluation of ECC in Single and Multi Processor Architectures on FPGA Based Embedded System S Agarwal, S Saha, R Paul, A Chakrabarti ICCN-2013 Bangalore,, 140-147, 2013 | 5 | 2013 |
| A brief experience on journey through hardware developments for image processing and its applications on Cryptography S Saha, S Maity, S Sau arXiv preprint arXiv:1212.6303, 2012 | 5 | 2012 |
| Architecture for real time continuous sorting on large width data volume for FPGA based applications R Paul, S Sau, A Chakrabarti arXiv preprint arXiv:1206.1567, 2012 | 5 | 2012 |
Amlan ChakrabartiProfessor and Director, A.K.Choudhury School of Information Technology, University ofVerified email at ieee.org
