| Memory sizing of a scalable SRAM in-memory computing tile based architecture R Gauchi, M Kooli, P Vivet, JP Noel, E Beigné, S Mitra, HP Charles 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 29 | 2019 |
| A 35.6 TOPS/W/mm² 3-stage pipelined computational SRAM with adjustable form factor for highly data-centric applications JP Noel, M Pezzin, R Gauchi, JF Christmann, M Kooli, HP Charles, ... IEEE Solid-State Circuits Letters 3, 286-289, 2020 | 21 | 2020 |
| Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization R Gauchi, V Egloff, M Kooli, JP Noel, B Giraud, P Vivet, S Mitra, ... Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020 | 12 | 2020 |
| Computational SRAM design automation using pushed-rule bitcells for energy-efficient vector processing JP Noel, V Egloff, M Kooli, R Gauchi, JM Portal, HP Charles, P Vivet, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 9 | 2020 |
| Towards a truly integrated vector processing unit for memory-bound applications based on a cost-competitive computational SRAM design solution M Kooli, A Heraud, HP Charles, B Giraud, R Gauchi, M Ezzadeen, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (2), 1-26, 2022 | 8 | 2022 |
| Storage class memory with computing row buffer: A design space exploration V Egloff, JP Noel, M Kooli, B Giraud, L Ciampolini, R Gauchi, C Fuguet, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2021 | 6 | 2021 |
| An open-source three-independent-gate fet standard cell library for mixed logic synthesis R Gauchi, A Snelgrove, PE Gaillardon 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 273-277, 2022 | 5 | 2022 |
| Low latency seu detection in fpga cram with in-memory ecc checking A Alacchi, E Giacomin, S Temple, R Gauchi, M Wirthlin, PE Gaillardon IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 4 | 2023 |
| Exploration of reconfigurable tiles of computing-in-memory architecture for data-intensive applications R Gauchi Université Grenoble Alpes [2020-....], 2021 | 2 | 2021 |
| An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing M Keyser, R Gauchi, PE Gaillardon 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration …, 2022 | 1 | 2022 |
| Secure eFPGA Configuration: A System-Level Approach A Boston, R Gauchi, PE Gaillardon International Symposium on Applied Reconfigurable Computing, 151-165, 2024 | | 2024 |
| Reconfigurable memory module designed to implement computing operations R Gauchi, P Vivet, S Mitra, H Charles US Patent App. 18/040,246, 2023 | | 2023 |
| Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures A Alacchi, E Giacomin, R Gauchi, S Kulis, PE Gaillardon IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | | 2023 |
| Memory module adapted to implementing computing functions M Kooli, R Gauchi, P Vivet US Patent 11,482,264, 2022 | | 2022 |
| Exploration d'une architecture tuilée reconfigurable de mémoire calculante pour les applications gourmandes en données R Gauchi Université Grenoble Alpes, 2021 | | 2021 |
| Qu’est-ce qu’un plan de gestion des données?(22/05/2020) JP Noel, V Egloff, M Kooli, R Gauchi, JM Portal Evolution 39, 973, 0 | | |
