Compact models of negative-capacitance FinFETs: Lumped and distributed charge models JP Duarte, S Khandelwal, AI Khan, A Sachid, YK Lin, HL Chang, ...
2016 IEEE International Electron Devices Meeting (IEDM), 30.5. 1-30.5. 4, 2016
102 2016 Engineering negative differential resistance in NCFETs for analog applications H Agarwal, P Kushwaha, JP Duarte, YK Lin, AB Sachid, MY Kao, ...
IEEE Transactions on Electron Devices 65 (5), 2033-2039, 2018
101 2018 Stress-induced hump effects of p-channel polycrystalline silicon thin-film transistors CF Huang, CY Peng, YJ Yang, HC Sun, HC Chang, PS Kuo, HL Chang, ...
IEEE Electron Device Letters 29 (12), 1332-1335, 2008
71 2008 Variation caused by spatial distribution of dielectric and ferroelectric grains in a negative capacitance field-effect transistor MY Kao, AB Sachid, YK Lin, YH Liao, H Agarwal, P Kushwaha, JP Duarte, ...
IEEE Transactions on Electron Devices 65 (10), 4652-4658, 2018
40 2018 Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved Sensitivity in Presence of Parasitic Capacitance H Agarwal, P Kushwaha, JP Duarte, YK Lin, AB Sachid, HL Chang, ...
IEEE Transactions on Electron Devices 65 (3), 1211-1216, 2018
33 2018 Physical mechanism of HfO2 -based bipolar resistive random access memory HL Chang, HC Li, CW Liu, F Chen, MJ Tsai
Proceedings of 2011 International Symposium on VLSI Technology, Systems and …, 2011
30 2011 BSIM-HV: High-voltage MOSFET model including quasi-saturation and self-heating effect H Agarwal, C Gupta, R Goel, P Kushwaha, YK Lin, MY Kao, JP Duarte, ...
IEEE Transactions on Electron Devices 66 (10), 4258-4263, 2019
26 2019 Coupling effects of dual SiGe power amplifiers for 802.11 n MIMO applications WC Hua, PT Lin, CP Lin, CY Lin, HL Chang, CW Liu, TY Yang, GK Ma
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006, 4 pp., 2006
23 2006 A predictive tunnel FET compact model with atomistic simulation validation YK Lin, S Khandelwal, JP Duarte, HL Chang, S Salahuddin, C Hu
IEEE Transactions on Electron Devices 64 (2), 599-605, 2016
22 2016 Effect of polycrystallinity and presence of dielectric phases on NC-FinFET variability YK Lin, MY Kao, H Agarwal, YH Liao, P Kushwaha, K Chatterjee, ...
2018 IEEE International Electron Devices Meeting (IEDM), 9.4. 1-9.4. 4, 2018
18 2018 Compact modeling source-to-drain tunneling in sub-10-nm GAA FinFET with industry standard model YK Lin, JP Duarte, P Kushwaha, H Agarwal, HL Chang, A Sachid, ...
IEEE Transactions on Electron Devices 64 (9), 3576-3581, 2017
17 2017 Modeling of advanced RF bulk FinFETs P Kushwaha, H Agarwal, YK Lin, MY Kao, JP Duarte, HL Chang, W Wong, ...
IEEE Electron Device Letters 39 (6), 791-794, 2018
16 2018 Modeling of Subsurface Leakage Current in Low Short Channel MOSFET at Accumulation Bias YK Lin, S Khandelwal, AS Medury, H Agarwal, HL Chang, YS Chauhan, ...
IEEE Transactions on Electron Devices 63 (5), 1840-1845, 2016
16 2016 Modeling of back-gate effects on gate-induced drain leakage and gate currents in UTB SOI MOSFETs YK Lin, P Kushwaha, H Agarwal, HL Chang, JP Duarte, AB Sachid, ...
IEEE Transactions on Electron Devices 64 (10), 3986-3990, 2017
15 2017 Negative-capacitance FinFETs: Numerical simulation, compact modeling and circuit evaluation JP Duarte, YK Lin, YH Liao, A Sachid, MY Kao, H Agarwal, P Kushwaha, ...
2018 International conference on simulation of semiconductor processes and …, 2018
13 2018 BSIM-BULK 106.2. 0 MOSFET Compact Model Technical Manual H Agarwal, C Gupta, HL Chang, S Khandelwal, JP Duarte, YS Chauhan, ...
Univ. California, Berkeley, 2017
12 2017 Improved SPICE macromodel of phase change random access memory HL Chang, HC Chang, SC Yang, HC Tsai, HC Li, CW Liu
2009 International Symposium on VLSI Design, Automation and Test, 134-137, 2009
10 2009 BSIM-BULK106. 2.0 Technical Manual H Agarwal, C Gupta, SKH Chang, JP Duarte, YS Chauhan, S Salahuddin, ...
University of California, Berkeley, CA, USA.[Online]. Available: http://bsim …, 2017
9 2017 Modeling of GeOI and validation with Ge-CMOS inverter circuit using BSIM-IMG industry standard model H Agarwal, P Kushwaha, YS Chauhan, S Khandelwal, JP Duarte, YK Lin, ...
2016 IEEE International Conference on Electron Devices and Solid-State …, 2016
9 2016 New mobility model for accurate modeling of transconductance in FDSOI MOSFETs YK Lin, P Kushwaha, JP Duarte, HL Chang, H Agarwal, S Khandelwal, ...
IEEE Transactions on Electron Devices 65 (2), 463-469, 2018
8 2018