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Belgacem BEN HEDIA
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Formal evaluation of quality of service for data acquisition systems
B Ben Hedia, F Jumel, JP Babau, CI Lyon-CPE
Proc. of FDL 5, 2005
19*2005
Formal Executable Models for Automatic Detection of Timing Anomalies
M Asavoae, B Ben Hedia, M Jan
18th International Workshop on Worst-Case Execution Time Analysis (WCET 2018), 2018
122018
Specifying and Verifying Concurrent C Programs with TLA+
A Methni, M Lemerre, B Ben Hedia, S Haddad, K Barkaoui
Formal Techniques for Safety-Critical Systems, 206-222, 2014
112014
Experiences and reflections on three years of CPS summer schools within EIT digital
D Cancila, V Nuzzo, M Stoycheva, W Birk, F Asplund, M Torngren
Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems …, 2016
82016
Towards time-triggered component-based system models
H Guesmi, BB Hedia, S Bliudze, S Bensalem, J Combaz
82015
Formal modelling framework of data acquisition modules using a synchronous approach for timing analysis
L Morel, JP Babau, B Ben Hedia
WRTP/RTS 1, 2009
52009
State space reduction strategies for model checking concurrent C programs
A Methni, BB Hedia, M Lemerre, S Haddad, K Barkaoui
9th Workshop on Verification and Evaluation of Computer and Communication …, 2015
42015
Scalable Detection of Amplification Timing Anomalies for the Superscalar TriCore Architecture
B Binder, M Asavoae, F Brandner, BB Hedia, M Jan
International Conference on Formal Methods for Industrial Critical Systems …, 2020
32020
Towards Formal Co-validation of Hardware and Software Timing Models of CPSs
M Asavoae, I Haur, M Jan, BB Hedia, M Schoeberl
Cyber Physical Systems. Model-Based Design, 203-227, 2019
32019
Towards Correct Transformation: From High-Level Models to Time-Triggered Implementations
H Guesmi, BB Hedia, S Bliudze, M Jan, S Bensalem
RTAS, 13, 2016
22016
Externalisation of Time-Triggered communication system in BIP high level models
H Guesmi, B Ben Hedia, S Bliudze, S Bensalem
JRWRTC 2014, 41, 2014
22014
Formal modeling and verification for amplification timing anomalies in the superscalar TriCore architecture
B Binder, M Asavoae, F Brandner, B Ben Hedia, M Jan
International Journal on Software Tools for Technology Transfer 24 (3), 415-440, 2022
12022
Formal Modeling and Verification for Timing Predictability
M Asavoae, M Jan, B Ben Hedia
ERTS, 2020
12020
QuaRTOS-DSE: A Tool for Design Space Exploration of Embedded Real-Time System
B Le Nabec, BB Hedia, JP Babau
2018 IEEE 21st International Symposium on Real-Time Distributed Computing …, 2018
12018
Towards an Ultra-lightweight Cryptosystem for IoT
T Omrani, L Sliman, R Becheikh, S Belghith, B Ben Hedia
International Conference on Soft Computing and Pattern Recognition, 614-621, 2016
12016
Modeling legacy code with BIP: how to reduce the gap between formal description and real-time implementation
B Le Nabec, BB Hedia, JP Babau, M Jan, H Guesmi
2016 Forum on Specification and Design Languages (FDL), 1-8, 2016
12016
Verifying and Constructing Abstract TLA Specifications: Application to the Verification of C programs
A Methni, M Lemerre, BB Hedia, S Haddad, K Barkaoui
12015
ANALYSE TEMPORELLE DES SYS-TÈMES D’ACQUISITION DE DONNÉES: UNE APPROCHE À BASE D’AUTO-MATES TEMPORISÉS COMMUNICANTS ET D’OBSERVATEURS
B BEN HEDIA
INSA-LYON, 2008
12008
Is This Still Normal? Putting Definitions of Timing Anomalies to the Test
B Binder, M Asavoae, BB Hedia, F Brandner, M Jan
2021 IEEE 27th International Conference on Embedded and Real-Time Computing …, 2021
2021
Verification and Evaluation of Computer and Communication Systems: 14th International Conference, VECoS 2020, Xi'an, China, October 26–27, 2020, Proceedings
BB Hedia, YF Chen, G Liu, Z Yu
Springer Nature, 2020
2020
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