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Ramesh Harjani
Ramesh Harjani
E. F. Johnson Professor, Electrical & Computer Engineering, University of Minnesota
Adresse e-mail validée de umn.edu - Page d'accueil
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OASYS: A framework for analog circuit synthesis
R Harjani, RA Rutenbar, LR Carley
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1989
6041989
A high-efficiency DC–DC converter using 2 nH integrated inductors
J Wibben, R Harjani
IEEE Journal of Solid-State Circuits 43 (4), 844-854, 2008
4072008
A low-power CMOS VGA for 50 Mb/s disk drive read channels
R Harjani
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1995
2831995
Design of low-phase-noise CMOS ring oscillators
L Dai, R Harjani
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2002
1692002
Fully-integrated on-chip DC-DC converter with a 450X output range
SS Kudva, R Harjani
IEEE Journal of Solid-State Circuits 46 (8), 1940-1951, 2011
1542011
A prototype framework for knowledge-based analog circuit synthesis
R Harjani, RA Rutenbar, LR Carley
Proceedings of the 24th ACM/IEEE Design Automation Conference, 42-49, 1987
1521987
Partial positive feedback for gain enhancement of low-power CMOS OTAs
R Wang, R Harjani
Low-Voltage Low-Power Analog Integrated Circuits: A Special Issue of Analog …, 1995
1401995
CMOS switched-op-amp-based sample-and-hold circuit
L Dai, R Harjani
IEEE journal of solid-state circuits 35 (1), 109-113, 2000
1372000
A+ 18 dBm IIP3 LNA in 0.35/spl mu/m CMOS
Y Ding, R Harjani
2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001
1262001
ALIGN: Open-source analog layout automation from the ground up
K Kunal, M Madhusudan, AK Sharma, W Xu, SM Burns, R Harjani, J Hu, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019
1152019
A linearized, low phase noise VCO based 25 GHz PLL with automatic biasing
B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, J Plouchart, AV Rylyakov, ...
IEEE Journal of Solid-State Circuits 48 (5), 1138-1150, 2013
1092013
Design of high-performance CMOS voltage-controlled oscillators
L Dai, R Harjani
Springer Science & Business Media, 2003
1022003
High-frequency LC VCO design using capacitive degeneration
B Jung, R Harjani
IEEE Journal of Solid-State Circuits 39 (12), 2359-2370, 2004
902004
A customized graph neural network model for guiding analog IC placement
Y Li, Y Lin, M Madhusudan, A Sharma, W Xu, SS Sapatnekar, R Harjani, ...
Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020
862020
A high-efficiency CMOS +22-dBm linear power amplifier
Y Ding, R Harjani
Solid-State Circuits, IEEE Journal of 40 (9), 1895-1900, 2005
852005
GANA: Graph convolutional network based automated netlist annotation for analog circuits
K Kunal, T Dhar, M Madhusudan, J Poojary, A Sharma, W Xu, SM Burns, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 55-60, 2020
842020
An integrated low-voltage class AB CMOS OTA
R Harjani, R Heineke, F Wang
IEEE Journal of Solid-State Circuits 34 (2), 134-142, 1999
781999
Feasibility and performance region modeling of analog and digital circuits
R Harjani, J Shao
Modeling and Simulation of Mixed Analog-Digital Systems, 23-43, 1996
781996
Time-encoded values for highly efficient stochastic circuits
MH Najafi, S Jamali-Zavareh, DJ Lilja, MD Riedel, K Bazargan, R Harjani
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (5 …, 2017
772017
Fully Integrated Capacitive DC–DC Converter With All-Digital Ripple Mitigation Technique
SS Kudva, R Harjani
IEEE Journal of Solid-State Circuits 48 (8), 1910-1920, 2013
742013
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