Souvik Mahapatra
Souvik Mahapatra
Professor, EE Dept, IIT Bombay (Fellow of IEEE, INSA, IASc, INAE)
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A comprehensive model of PMOS NBTI degradation
MA Alam, S Mahapatra
Microelectronics Reliability 45 (1), 71-81, 2005
A comprehensive model for PMOS NBTI degradation: Recent progress
MA Alam, H Kufluoglu, D Varghese, S Mahapatra
Microelectronics Reliability 47 (6), 853-862, 2007
Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation
AE Islam, H Kufluoglu, D Varghese, S Mahapatra, MA Alam
IEEE Transactions on Electron Devices 54 (9), 2143-2154, 2007
Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs
S Mahapatra, PB Kumar, MA Alam
IEEE Transactions on Electron Devices 51 (9), 1371-1379, 2004
A comparative study of different physics-based NBTI models
S Mahapatra, N Goel, S Desai, S Gupta, B Jose, S Mukhopadhyay, ...
IEEE Transactions on Electron Devices 60 (3), 901-916, 2013
On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress
S Mahapatra, D Saha, D Varghese, PB Kumar
IEEE Transactions on Electron Devices 53 (7), 1583-1592, 2006
On the physical mechanism of NBTI in silicon oxynitride p-MOSFETs: Can differences in insulator processing conditions resolve the interface trap generation versus hole trapping …
S Mahapatra, K Ahmed, D Varghese, AE Islam, G Gupta, L Madhav, ...
2007 IEEE International Reliability Physics Symposium Proceedings. 45th …, 2007
On the dispersive versus Arrhenius temperature activation of NBTI time evolution in plasma nitrided gate oxides: Measurements, theory, and implications
D Varghese, D Saha, S Mahapatra, K Ahmed, F Nouri, M Alam
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
A critical re-evaluation of the usefulness of RD framework in predicting NBTI stress and recovery
S Mahapatra, AE Islam, S Deora, VD Maheta, K Joshi, A Jain, MA Alam
2011 International Reliability Physics Symposium, 6A. 3.1-6A. 3.10, 2011
Critical Role of Interlayer in Hf0.5Zr0.5O2Ferroelectric FET Nonvolatile Memory Performance
K Ni, P Sharma, J Zhang, M Jerry, JA Smith, K Tapily, R Clark, ...
IEEE Transactions on Electron Devices, 2018
A consistent physical framework for N and P BTI in HKMG MOSFETs
K Joshi, S Mukhopadhyay, N Goel, S Mahapatra
2012 IEEE international reliability physics symposium (IRPS), 5A. 3.1-5A. 3.10, 2012
Isolation of NBTI stress generated interface trap and hole-trapping components in PNO p-MOSFETs
S Mahapatra, VD Maheta, AE Islam, MA Alam
IEEE Transactions on Electron Devices 56 (2), 236-242, 2009
Mechanism of negative bias temperature instability in CMOS devices: degradation, recovery and impact of nitrogen
S Mahapatra, PB Kumar, TR Dalei, D Sana, MA Alam
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
A predictive reliability model for PMOS bias temperature degradation
S Mahapatra, MA Alam
Digest. International Electron Devices Meeting,, 505-508, 2002
Defect generation in p-MOSFETs under negative-bias stress: An experimental perspective
S Mahapatra, MA Alam
IEEE Transactions on Device and Materials Reliability 8 (1), 35-46, 2008
Negative bias temperature instability in CMOS devices
S Mahapatra, MA Alam, PB Kumar, TR Dalei, D Varghese, D Saha
Microelectronic engineering 80, 114-121, 2005
CHISEL flash EEPROM. I. Performance and scaling
S Mahapatra, S Shukuri, J Bude
IEEE Transactions on Electron Devices, 2002
Hole energy dependent interface trap generation in MOSFET Si/SiO/sub 2/interface
D Varghese, S Mahapatra, MA Alam
IEEE electron device letters 26 (8), 572-574, 2005
BTI Analysis Tool—Modeling of NBTI DC, AC Stress and Recovery Time Kinetics, Nitrogen Impact, and EOL Estimation
N Parihar, N Goel, S Mukhopadhyay, S Mahapatra
IEEE Transactions on Electron Devices, 2018
Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs
S Mahapatra, CD Parikh, VR Rao, CR Viswanathan, J Vasi
IEEE Transactions on Electron Devices 47 (4), 789-796, 2000
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