| 14.1 A 2.9 TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems G Desoli, N Chawla, T Boesch, S Singh, E Guidetti, F De Ambroggi, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 238-239, 2017 | 166 | 2017 |
| Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry A Bhuvanagiri, H Singh, R Malik, N Chawla US Patent 7,698,355, 2010 | 12 | 2010 |
| A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver P Busson, N Chawla, J Bach, S Le Tual, H Singh, V Gupta, P Urard 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 3 | 2009 |
| A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit P Busson, N Chawla, JÉÔ Bach, S Le Tual, H Singh, V Gupta, P Urard IEEE journal of solid-state circuits 45 (1), 84-94, 2009 | 1 | 2009 |
| ISSCC 2017/SESSION 14/DEEP-LEARNING PROCESSORS/14.1 G Desoli, N Chawla, T Boesch, S Singh, E Guidetti, F De Ambroggi, ... | | |
