| Bit-parallel systolic multipliers for GF(2^m) fields defined by all-one and equally spaced polynomials CY Lee, EH Lu, JY Lee Computers, IEEE Transactions on 50 (5), 385-393, 2001 | 221 | 2001 |
| Low-complexity bit-parallel systolic Montgomery multipliers for special classes of GF(2^m) CY Lee, JS Horng, IC Jou, EH Lu Computers, IEEE Transactions on 54 (9), 1061-1070, 2005 | 148 | 2005 |
| Novel systolization of subquadratic space complexity multipliers based on toeplitz matrix–vector product approach JS Pan, CY Lee, A Sghaier, M Zeghid, J Xie IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (7 …, 2019 | 132 | 2019 |
| Concurrent Error Detection in Montgomery Multiplication over GF(2^m) CW Chiou, LEE Chiou-Yng, D An-Wen, LIN Jim-Min IEICE Transactions on Fundamentals of Electronics, Communications and …, 2006 | 98 | 2006 |
| Low complexity bit-parallel systolic multiplier over GF (2m) using irreducible trinomials CY Lee IEE Proceedings-Computers and Digital Techniques 150 (1), 39-42, 2003 | 85 | 2003 |
| Efficient Design of Low-Complexity Bit-Parallel Systolic Hankel Multipliers to Implement Multiplication in Normal and Dual Bases of GF (2^m) LEE Chiou-Yng, CW Chiou IEICE Transactions on Fundamentals of Electronics, Communications and …, 2005 | 67 | 2005 |
| Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields JS Pan, CY Lee, PK Meher IEEE Transactions on Circuits and Systems-I: regular papers 60 (12), 125 – 129, 2013 | 63 | 2013 |
| Concurrent Error Detection in a Polynomial Basis Multiplier over GF (2^m) CY Lee, CW Chiou, JM Lin Journal of Electronic Testing 22 (2), 143-150, 2006 | 60 | 2006 |
| Low-complexity bit-parallel systolic architecture for computing AB/sup 2/+ C in a class of finite field GF (2/sup m/) CY Lee, EH Lu, LF Sun IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001 | 59 | 2001 |
| Concurrent error detection and correction in Gaussian normal basis multiplier over GF (2^ m) CW Chiou, CC Chang, CY Lee, TW Hou, JM Lin IEEE Transactions on Computers 58 (6), 851-857, 2008 | 52 | 2008 |
| Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2 m ) CY Lee, CW Chiou, JM Lin Journal of Electronic Testing 21, 539-549, 2005 | 51 | 2005 |
| Scalable Gaussian normal basis multipliers over GF(2^m) using Hankel matrix-vector representation CY Lee, CW Chiou Journal of Signal Processing Systems 69 (2), 197-211, 2012 | 50 | 2012 |
| Scalable and systolic Montgomery multiplier over generated by trinomials CY Lee, CW Chiou, JM Lin, CC Chang Circuits, Devices & Systems, IET 1 (6), 477-484, 2007 | 49 | 2007 |
| Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over M Mozaffari-Kermani, R Azarderakhsh, CY Lee, S Bayat-Sarmadi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (5), 995 …, 2013 | 40 | 2013 |
| Low-latency digit-serial systolic double basis multiplier over GF (2m) using subquadratic Toeplitz matrix-vector product approach JS Pan, R Azarderakhsh, MM Kermani, CY Lee, WY Lee, CW Chiou, ... IEEE Transactions on Computers 63 (5), 1169 - 1181, 2014 | 39* | 2014 |
| Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition CY Lee, CS Yang, BK Meher, PK Meher, JS Pan IEEE Transactions on Circuits and Systems-I: regular papers 61 (11), 3115 - 3124, 2014 | 36 | 2014 |
| Computation of AB^2 Multiplier in GF (2^m) Using an Efficient Low-Complexity Cellular Architecture LIU Chung-Hsin, NF Huang, LEE Chiou-Yng IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2000 | 36 | 2000 |
| Multiplexer-based double-exponentiation for normal basis of GF(2^m) CW Chiou, CY Lee Computers & Security 24 (1), 83-86, 2005 | 34 | 2005 |
| Low-Latency Bit-Parallel Systolic Multiplier for Irreducible x^m+x^n+ 1 with GCD( m, n)= 1 LEE Chiou-Yng IEICE Transactions on Fundamentals of Electronics, Communications and …, 2003 | 33 | 2003 |
| Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures S Bayat-Sarmadi, M Mozaffari Kermani, R Azarderakhsh, CY Lee IEEE Transactions on Circuits and Systems-II 61 (2), 125 – 129, 2014 | 31 | 2014 |
Pramod MeherC V Raman Global University, Bhubaneswar, IndiaVerified email at sandhaanlabs.in
