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Jean-Francois de Marneffe
Jean-Francois de Marneffe
Principal Member of Technical Staff at imec vzw
Verified email at imec.be - Homepage
Title
Cited by
Cited by
Year
Plasma processing of low-k dielectrics
MR Baklanov, JF de Marneffe, D Shamiryan, AM Urbanowicz, H Shi, ...
Journal of Applied Physics 113 (4), 2013
3502013
Multilayer MoS 2 growth by metal and metal oxide sulfurization
MH Heyne, D Chiappe, J Meersschaut, T Nuytten, T Conard, H Bender, ...
Journal of Materials Chemistry C 4 (6), 1295-1304, 2016
682016
Performance improvement of tall triple gate devices with strained SiN layers
N Collaert, A De Keersgieter, KG Anil, R Rooyackers, G Eneman, ...
IEEE electron device letters 26 (11), 820-822, 2005
662005
Demonstration of fully Ni-silicided metal gates on HfO/sub 2/based high-k gate dielectrics as a candidate for low power applications
KG Anil, A Veloso, S Kubicek, T Schram, E Augendre, JF de Marneffe, ...
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 190-191, 2004
492004
Defect-induced bandgap narrowing in low-k dielectrics
X Guo, H Zheng, SW King, VV Afanas' ev, MR Baklanov, JF de Marneffe, ...
Applied Physics Letters 107 (8), 2015
462015
On the scalability of source/drain current enhancement in thin film sSOI
E Augendre, G Eneman, A De Keersgieter, V Simons, I De Wolf, J Ramos, ...
Proceedings of 35th European Solid-State Device Research Conference, 2005 …, 2005
422005
Low damage cryogenic etching of porous organosilicate low-k materials using SF6/O2/SiF4
L Zhang, R Ljazouli, P Lefaucheux, T Tillocher, R Dussart, ...
ECS Journal of Solid State Science and Technology 2 (6), N131, 2013
402013
Damage free cryogenic etching of a porous organosilica ultralow-k film
L Zhang, R Ljazouli, P Lefaucheux, T Tillocher, R Dussart, ...
ECS Solid State Letters 2 (2), N5, 2012
392012
Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab
I Asselberghs, Q Smets, T Schram, B Groven, D Verreck, A Afzalian, ...
2020 IEEE International Electron Devices Meeting (IEDM), 40.2. 1-40.2. 4, 2020
352020
Damage free integration of ultralow-k dielectrics by template replacement approach
L Zhang, JF De Marneffe, N Heylen, G Murdoch, Z Tokei, J Boemmels, ...
Applied Physics Letters 107 (9), 2015
352015
Deviations from plastic barriers in thin films
YZ Zhang, Z Wang, XF Lu, HH Wen, JF De Marneffe, R Deltour, ...
Physical Review B 71 (5), 052502, 2005
342005
Effect of UV irradiation on modification and subsequent wet removal of model and post-etch fluorocarbon residues
QT Le, JF de Marneffe, T Conard, I Vaesen, H Struyf, G Vereecke
Journal of The Electrochemical Society 159 (3), H208, 2011
332011
Reactive plasma cleaning and restoration of transition metal dichalcogenide monolayers
D Marinov, JF de Marneffe, Q Smets, G Arutchelvan, KM Bal, E Voronina, ...
npj 2D Materials and Applications 5 (1), 17, 2021
322021
Improved plasma resistance for porous low-k dielectrics by pore stuffing approach
L Zhang, JF de Marneffe, MH Heyne, S Naumov, Y Sun, A Zotovich, ...
ECS Journal of Solid State Science and Technology 4 (1), N3098, 2014
322014
Etching of low-k materials for microelectronics applications by means of a N2/H2 plasma: modeling and experimental investigation
K Van Laer, S Tinck, V Samara, JF de Marneffe, A Bogaerts
Plasma Sources Science and Technology 22 (2), 025011, 2013
292013
A 0.314/spl mu/m/sup 2/6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75 NA 193nm lithography
A Nackaerts, M Ercken, S Demuynck, A Lauwers, C Baerts, H Bender, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
292004
Imaging performance of the EUV alpha semo tool at IMEC
GF Lorusso, J Hermans, AM Goethals, B Baudemprez, F Van Roey, ...
Emerging Lithographic Technologies XII 6921, 202-211, 2008
282008
Molecular glass resists for scanning probe lithography
C Neuber, A Ringk, T Kolb, F Wieberger, P Strohriegl, HW Schmidt, ...
Alternative Lithographic Technologies VI 9049, 375-383, 2014
272014
Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices
S Severi, KG Anil, K Henson, A Lauwers, A Veloso, JF de Marneffe, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
272004
Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs
A Veloso, KG Anil, L Witters, S Brus, S Kubicek, JF de Marneffe, B Sijmus, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
272004
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