Benoit Larras
Benoit Larras
Associate Professor, SMART Departement, ISEN Lille / IEMN
Adresse e-mail validée de yncrea.fr
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Analog implementation of encoded neural networks
B Larras, C Lahuec, M Arzel, F Seguin
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 1612-1615, 2013
152013
Ultra-low-energy mixed-signal ic implementing encoded neural networks
B Larras, C Lahuec, F Seguin, M Arzel
IEEE Transactions on Circuits and Systems I: Regular Papers 63 (11), 1974-1985, 2016
142016
Analog encoded neural network for power management in MPSoC
B Larras, B Boguslawski, C Lahuec, M Arzel, F Seguin, F Heitzmann
Analog Integrated Circuits and Signal Processing 81 (3), 595-605, 2014
132014
Energy-Efficient Associative Memory Based on Neural Cliques
B Boguslawski, F Heitzmann, B Larras, F Seguin
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (4), 376-380, 2015
72015
A fully flexible circuit implementation of clique-based neural networks in 65-nm CMOS
B Larras, P Chollet, C Lahuec, F Seguin, M Arzel
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (5), 1704-1715, 2018
32018
Design of analog subthreshold encoded neural network circuit in sub-100nm cmos
B Larras, C Lahuec, F Seguin, M Arzel
2015 International Joint Conference on Neural Networks (IJCNN), 1-7, 2015
32015
Low-complexity feature extraction unit for “Wake-on-Feature” speech processing
S Lecoq, J Le Bellego, A Gonzalez, B Larras, A Frappé
2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018
12018
An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS
P Chollet, B Larras, C Lahuec, F Seguin, M Arzel
2017 15th IEEE International New Circuits and Systems Conference (NEWCAS), 5-8, 2017
12017
A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture
B Larras, P Chollet, C Lahuec, F Seguin, M Arzel
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
12017
A Wide Tuning Range Delay Element for Event-Driven Processing of Low-Frequency Signals in 28-nm FD-SOI CMOS
A González, A Frappé, B Larras, A Kaiser, P Cathelin
IEEE Solid-State Circuits Letters 3, 198-201, 2020
2020
Distributed Clique-Based Neural Networks for Data Fusion at the Edge
B Larras, A Frappé
2020 2nd IEEE International Conference on Artificial Intelligence Circuits …, 2020
2020
Intégration CMOS analogique de réseaux de neurones à cliques
B Larras
2015
SPECIAL ISSUE ON THE 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2018)
A Ergintav, F Herzel, G Fischer, D Kissinger, S Kalani, T Haque, R Gupta, ...
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