Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ...
2017 symposium on VLSI technology, T230-T231, 2017
768 2017 0.13 G Avenier, M Diop, P Chevalier, G Troillard, N Loubet, J Bouvier, ...
IEEE journal of solid-state circuits 44 (9), 2312-2321, 2009
176 2009 A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ...
2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016
174 2016 Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, J Kuss, D Shahrjerdi, ...
2009 IEEE international electron devices meeting (IEDM), 1-4, 2009
172 2009 FDSOI devices with thin BOX and ground plane integration for 32 nm node and below C Fenouillet-Beranger, S Denorme, P Perreau, C Buj, O Faynot, F Andrieu, ...
Solid-State Electronics 53 (7), 730-734, 2009
163 2009 High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET K Cheng, A Khakifirooz, N Loubet, S Luning, T Nagumo, M Vinet, Q Liu, ...
2012 International Electron Devices Meeting, 18.1. 1-18.1. 4, 2012
124 2012 High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond Q Liu, M Vinet, J Gimbert, N Loubet, R Wacquez, L Grenouillet, Y Le Tiec, ...
2013 IEEE International Electron Devices Meeting, 9.2. 1-9.2. 4, 2013
118 2013 14nm FDSOI technology for high speed and energy efficient applications O Weber, E Josse, F Andrieu, A Cros, E Richard, P Perreau, E Baylac, ...
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
112 2014 Method of forming a fully substrate-isolated FinFET transistor N Loubet, P Khare
US Patent 8,956,942, 2015
105 2015 Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond Q Liu, A Yagishita, N Loubet, A Khakifirooz, P Kulkarni, T Yamamoto, ...
2010 Symposium on VLSI Technology, 61-62, 2010
91 2010 Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm2 6T-SRAM bitcell C Fenouillet-Beranger, S Denorme, B Icard, F Boeuf, J Coignus, O Faynot, ...
2007 IEEE International Electron Devices Meeting, 267-270, 2007
84 2007 Defect-free strain relaxed buffer layer P Morin, K Cheng, J Fronheiser, X Cai, J Li, S Mochizuki, R Xie, H He, ...
US Patent App. 14/588,221, 2016
79 2016 Channel geometry impact and narrow sheet effect of stacked nanosheet CW Yeung, J Zhang, R Chao, O Kwon, R Vega, G Tsutsui, X Miao, ...
2018 IEEE international electron devices meeting (IEDM), 28.6. 1-28.6. 4, 2018
76 2018 Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance I Lauer, N Loubet, SD Kim, JA Ott, S Mignot, R Venigalla, T Yamashita, ...
2015 Symposium on VLSI Technology (VLSI Technology), T140-T141, 2015
74 2015 Impact of back bias on ultra-thin body and BOX (UTBB) devices Q Liu, F Monsieur, A Kumar, T Yamamoto, A Yagishita, P Kulkarni, ...
2011 Symposium on VLSI Technology-Digest of Technical Papers, 160-161, 2011
73 2011 A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around nanosheet devices N Loubet, S Kal, C Alix, S Pancharatnam, H Zhou, C Durfee, M Belyansky, ...
2019 IEEE International Electron Devices Meeting (IEDM), 11.4. 1-11.4. 4, 2019
68 2019 FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
65 2016 Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ...
2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019
64 2019 UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below L Grenouillet, M Vinet, J Gimbert, B Giraud, JP Noel, Q Liu, P Khare, ...
2012 International Electron Devices Meeting, 3.6. 1-3.6. 4, 2012
62 2012 Method to co-integrate SiGe and Si channels for finFET devices N Loubet, P Khare, Q Liu
US Patent 9,685,380, 2017
59 2017 