| 14.1 A 2.9 TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems G Desoli, N Chawla, T Boesch, S Singh, E Guidetti, F De Ambroggi, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 238-239, 2017 | 166 | 2017 |
| A 360mW 105Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes enabling satellite-transmission portable devices P Urard, L Paumier, V Heinrich, N Raina, N Chawla 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 49 | 2008 |
| Deep convolutional network heterogeneous architecture G Desoli, T Boesch, N Chawla, SP Singh, E Guidetti, FG De Ambroggi, ... US Patent App. 15/423,272, 2018 | 43 | 2018 |
| Spread spectrum clock generation N Chawla US Patent 8,037,336, 2011 | 32 | 2011 |
| Fail safe adaptive voltage/frequency system N Chawla, C Parthasarathy, K Chatterjee, P Kumar US Patent 8,154,335, 2012 | 17 | 2012 |
| Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry A Bhuvanagiri, H Singh, R Malik, N Chawla US Patent 7,698,355, 2010 | 12 | 2010 |
| Artificial Intelligence: Why moving it to the Edge? J Hartmann, P Cappelletti, N Chawla, F Arnaud, A Cathelin ESSDERC 2021-IEEE 51st European Solid-State Device Research Conference …, 2021 | 8 | 2021 |
| Atypical presentations of melioidosis in North India: report of two cases G Garg, N Chawla, K Chawla, P Khosla, S Jain Journal of The Association of Physicians of India 63, 2015 | 8 | 2015 |
| Leveraging sequential equivalence checking to enable system-level to RTL flows P Urard, A Maalej, R Guizzetti, N Chawla Proceedings of the 45th annual Design Automation Conference, 816-821, 2008 | 8 | 2008 |
| Tagged memory operated at lower vmin in error tolerant system N Chawla, G Desoli, A Grover, T Boesch, SP Singh, M Ayodhyawasi US Patent 11,360,667, 2022 | 7 | 2022 |
| 14.1 a 2.9 tops/w deep convolutional neural network soc in fd-soi 28nm for intelligent embedded systems, in 2017 IEEE International Solid-State Circuits Conference (ISSCC) G Desoli, N Chawla, T Boesch, S Singh, E Guidetti, F De Ambroggi, ... IEEE, 2017 | 7 | 2017 |
| Calibration arrangement N Chawla, K Chatterjee, C Parthasarathy US Patent 9,021,324, 2015 | 7 | 2015 |
| Cloud Computing Strategy: Journey to Adoption of cloud N Chawla, D Kumar Proc. National Conference on Computing Communication and Information …, 2015 | 7 | 2015 |
| Structural modeling of implementation enablers of cloud computing N Chawla, D Kumar Advances in Computer and Computational Sciences: Proceedings of ICCCCS 2016 …, 2018 | 6 | 2018 |
| Fail safe adaptive voltage/frequency system N Chawla, C Parthasarathy, K Chatterjee, P Kumar US Patent 8,269,545, 2012 | 6 | 2012 |
| Multimedia application specific engine design using high level synthesis N Chawla, R Guizzetti, Y Meroth, A Deleule, V Gupta, V Kathail, P Urard Proc. DesignCon 2008, 2008 | 6 | 2008 |
| Desktop virtualization—Desktop as a service and formulation of TCO with return on investment N Chawla, D Kumar Software Engineering: Proceedings of CSI 2015, 599-608, 2019 | 5 | 2019 |
| Enablement of Internet of things using cloud computing N Chawla, D Kumar 2017 3rd International Conference on Computational Intelligence …, 2017 | 5 | 2017 |
| Cloud computing in smarter homes: enablement of internet of things DK Sharma, N Chawla, D Kumar Review of Business and Technology Research 12 (1), 34-39, 2015 | 5 | 2015 |
| Device for implementing a sum of products expression A Bhuvanagiri, R Malik, N Chawla US Patent 7,917,569, 2011 | 5 | 2011 |
