Open cell library in 15nm freepdk technology M Martins, JM Matos, RP Ribas, A Reis, G Schlinker, L Rech, J Michelsen
Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015
245 2015 Effective logic synthesis for threshold logic circuit design A Neutzling, JM Matos, A Mishchenko, A Reis, RP Ribas
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
22 2018 Threshold logic synthesis based on cut pruning A Neutzling, JM Matos, AI Reis, RP Ribas, A Mishchenko
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 494-499, 2015
22 2015 maj- Logic Synthesis for Emerging Technology A Neutzling, FS Marranghello, JM Matos, A Reis, RP Ribas
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
15 2019 Efficiently mapping VLSI circuits with simple cells JM Matos, J Carrabina, A Reis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
9 2018 Optimization on cell-library design for digital Application Specific Printed Electronics Circuits M Llamas, M Mashayekhi, J Carrabina, J Matos, A Reis
2014 24th International Workshop on Power and Timing Modeling, Optimization …, 2014
6 2014 Exact benchmark circuits for logic synthesis WL Neto, VN Possani, FS Marranghello, JM Matos, PE Gaillardon, AI Reis, ...
IEEE Design & Test 37 (3), 51-58, 2019
5 2019 Dataset for: effective logic synthesis flow for threshold logic circuit design A Neutzling, JM Matos, A Mishchenko, AI Reis, RP Ribas
Mendeley Data, v1, 2017
5 2017 A benchmark suite to jointly consider logic synthesis and physical design JM Matos, A Neutzling, RP Ribas, A Reis
Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015
5 2015 Physical awareness starting at technology-independent logic synthesis AI Reis, JMA Matos
Advanced Logic Synthesis, 69-101, 2018
4 2018 Deriving reduced transistor count circuits from AIGs JM Matos, M Ritt, R Ribas, A Reis
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 1-7, 2014
4 2014 Mapping circuits with simple cells from XOR-and-inverter graphs JM Matos, MH Backes, M Ritt, RP Ribas, A Reis
Proc. Int. Workshop Logic Synth.(IWLS), 75-82, 2015
3 2015 Graph based algorithms to efficiently map VLSI circuits with simple cells JMA Matos
2 2018 Reviewing AIG Equivalence Checking Approaches M Backes, JM Matos, R Ribas, A Reis
Proceedings of the ACM Microelectronics Student Forum, 1-4, 2014
2 2014 Banco de Dados na TV Digital Usando NuSOAP e NCLua SOAP TF SILVA, KS ALMEIDA, JMA MATOS, CS ALMEIDA, TS OLIVEIRA
Escola Regional Bahia, Alagoas e Sergipe SBC, 2011
1 2011 Exact multi-level benchmark circuit generation for logic synthesis evaluation WL Neto, VN Possani, FS Marranghello, JM Matos, AI Reis, RP Ribas
2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2018
2018 Technology Mapping for Circuits with Simple Cells JM Matos, A Reis, J Carrabina
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
2018 Polarity-Oriented AIG Rewriting for XOR/XNOR MH BACKES, JMA MATOS, RP RIBAS, AI REIS
South Symposium on Microelectronics, 2014
2014 A Case Study on ipPROCESS: IP-core Design in Academic Environment JCN Bittencourt, JMA Matos, AM Dias, NA Ferreira Neto
IBERCHIP XX Workshop, 2014
2014 Graph-based algorithms for transistor count minimization in VLSI circuit EDA tools JMA Matos
2014