David Hély
David Hély
Univ. Grenoble Alpes, Grenoble INP, LCIS
Adresse e-mail validée de lcis.grenoble-inp.fr
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Scan design and secure chip
D Hely, ML Flottes, F Bancel, B Rouzeyre, N Berard, M Renovell
IOLTS'04: 10th International On-Line Testing Symposium, 219-224, 2004
Test control for secure scan designs
D Hely, F Bancel, ML Flottes, B Rouzeyre
European Test Symposium (ETS'05), 190-195, 2005
Secure scan techniques: a comparison
D Hely, F Bancel, ML Flottes, B Rouzeyre
12th IEEE International On-Line Testing Symposium (IOLTS'06), 6 pp., 2006
Securing scan control in crypto chips
D Hély, F Bancel, ML Flottes, B Rouzeyre
Journal of Electronic Testing 23 (5), 457-464, 2007
Run-time detection of hardware Trojans: The processor protection unit
J Dubeuf, D Hély, R Karri
2013 18th IEEE European Test Symposium (ETS), 1-6, 2013
Key reconciliation protocols for error correction of silicon PUF responses
B Colombier, L Bossuet, V Fischer, D Hély
IEEE Transactions on Information Forensics and Security 12 (8), 1988-2002, 2017
RFID System On-line Testing based on the evaluation of the Tags Read-Error-Rate
G Fritz, V Beroulle, MD Nguyen, D Hély
Journal of Electronic Testing 27 (3), 267-276, 2011
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks
A Papadimitriou, D Hély, V Beroulle, P Maistri, R Leveugle
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
SALWARE: Salutary Hardware to design Trusted IC.
L Bossuet, D Hely
A secure scan design methodology
D Hély, F Bancel, ML Flottes, B Rouzeyre
Proceedings of the Design Automation & Test in Europe Conference 1, 1-2, 2006
Voltage glitch attacks on mixed-signal systems
N Beringuier-Boher, K Gomina, D Hely, JB Rigaud, V Beroulle, A Tria, ...
2014 17th Euromicro Conference on Digital System Design, 379-386, 2014
Reduction of interconnect delay by exploiting cross-talk
S Van Dijk, D Hely
Proceedings of the 27th European Solid-State Circuits Conference, 301-304, 2001
Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model
JM Dutertre, V Beroulle, P Candelier, S De Castro, LB Faber, ML Flottes, ...
2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 1-6, 2018
Secure and flexible trace-based debugging of systems-on-chip
J Backer, D Hely, R Karri
ACM Transactions on Design Automation of Electronic Systems (TODAES) 22 (2 …, 2016
Laser-induced fault effects in security-dedicated circuits
R Leveugle, P Maistri, P Vanhauwaert, F Lu, G Di Natale, ML Flottes, ...
2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC …, 2014
On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks
J Backer, D Hély, R Karri
2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2015
Secure design-for-debug for systems-on-chip
J Backer, D Hély, R Karri
2015 IEEE International Test Conference (ITC), 1-8, 2015
Method and device for detecting an erroneous jump during program execution
F Bancel, N Berard, D Hely
US Patent 8,495,734, 2013
Facilitating side channel analysis by obfuscation for Hardware Trojan detection
A Nejat, D Hely, V Beroulle
2015 10th International Design & Test Symposium (IDT), 129-134, 2015
EPC Class 1 GEN 2 UHF RFID tag emulator for robustness evaluation and improvement
O Abdelmalek, D Hély, V Beroulle
2013 8th International Conference on Design & Technology of Integrated …, 2013
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