Vincent Delaye
Vincent Delaye
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A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration
A Hubert, E Nowak, K Tachi, V Maffini-Alvaro, C Vizioz, C Arvet, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Novel integration process and performances analysis of Low STandby Power (LSTP) 3D Multi-Channel CMOSFET (MCFET) on SOI with Metal/High-K Gate stack
E Bernard, T Ernst, B Guillaumot, N Vulliet, V Barral, V Maffini-Alvaro, ...
2008 Symposium on VLSI Technology, 16-17, 2008
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
F Andrieu, O Weber, J Mazurier, O Thomas, JP Noel, ...
2010 Symposium on VLSI Technology, 57-58, 2010
Strain-induced performance enhancement of trigate and omega-gate nanowire FETs scaled down to 10-nm width
R Coquand, M Casse, S Barraud, D Cooper, V Maffini-Alvaro, ...
IEEE Transactions on Electron Devices 60 (2), 727-732, 2012
Chemical and structural properties of conducting nanofilaments in TiN/HfO2-based resistive switching structures
P Calka, E Martinez, V Delaye, D Lafond, G Audoit, D Mariolle, ...
Nanotechnology 24 (8), 085706, 2013
Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack
T Ernst, C Dupre, C Isheden, E Bernard, R Ritzenthaler, V Maffini-Alvaro, ...
2006 International Electron Devices Meeting, 1-4, 2006
First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers
L Brunet, P Batude, C Fenouillet-Béranger, P Besombes, L Hortemel, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
Growth and structural properties of step-graded, high Sn content GeSn layers on Ge
J Aubin, JM Hartmann, A Gassenq, JL Rouviere, E Robin, V Delaye, ...
Semiconductor Science and Technology 32 (9), 094006, 2017
Hydrogen annealing of arrays of planar and vertically stacked Si nanowires
E Dornel, T Ernst, JC Barbé, JM Hartmann, V Delaye, F Aussenac, ...
Applied Physics Letters 91 (23), 233502, 2007
Stacking fault generation during relaxation of silicon germanium on insulator layers obtained by the Ge condensation technique
B Vincent, JF Damlencourt, V Delaye, R Gassilloud, L Clavelier, Y Morand
Applied physics letters 90 (7), 074101, 2007
Evolution of Cu microstructure and resistivity during thermal treatment of damascene line: Influence of line width and temperature
V Carreau, S Maîtrejean, M Verdier, Y Bréchet, A Roule, A Toffoli, ...
Microelectronic Engineering 84 (11), 2723-2728, 2007
GeSn heterostructure micro-disk laser operating at 230 K
QM Thai, N Pauc, J Aubin, M Bertrand, J Chrétien, V Delaye, A Chelnokov, ...
Optics express 26 (25), 32500-32508, 2018
Trade-off between SET and data retention performance thanks to innovative materials for phase-change memory
G Navarro, M Coue, A Kiouseloglou, P Noe, F Fillot, V Delaye, A Persico, ...
2013 IEEE International Electron Devices Meeting, 21.5. 1-21.5. 4, 2013
Sb-doped GeS2as performance and reliability booster in Conductive Bridge RAM
E Vianello, G Molas, F Longnos, P Blaise, E Souchier, C Cagli, G Palma, ...
2012 International Electron Devices Meeting, 31.5. 1-31.5. 4, 2012
Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires
K Tachi, M Casse, D Jang, C Dupre, A Hubert, N Vulliet, V Maffini-Alvaro, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Properties of electrodeposited CuSCN 2D layers and nanowires influenced by their mixed domain structure
D Aldakov, C Chappaz-Gillot, R Salazar, V Delaye, KA Welsby, V Ivanova, ...
The Journal of Physical Chemistry C 118 (29), 16095-16103, 2014
Polymer solar cells with electrodeposited CuSCN nanowires as new efficient hole transporting layer
C Chappaz-Gillot, S Berson, R Salazar, B Lechêne, D Aldakov, V Delaye, ...
Solar energy materials and solar cells 120, 163-167, 2014
Strain mapping at the nanoscale using precession electron diffraction in transmission electron microscope with off axis camera
MP Vigouroux, V Delaye, N Bernier, R Cipro, D Lafond, G Audoit, T Baron, ...
Applied Physics Letters 105 (19), 191906, 2014
3D nanowire gate-all-around transistors: Specific integration and electrical features
C Dupré, T Ernst, V Maffini-Alvaro, V Delaye, JM Hartmann, S Borel, ...
Solid-State Electronics 52 (4), 519-525, 2008
Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications
G Piccolboni, G Molas, JM Portal, R Coquand, M Bocquet, D Garbin, ...
2015 IEEE International Electron Devices Meeting (IEDM), 17.2. 1-17.2. 4, 2015
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