| 16.8 A 25.4-to-29.5 GHz 10.2 mW isolated sub-sampling PLL achieving-252.9 dB jitter-power FoM and-63dBc reference spur Z Yang, Y Chen, S Yang, PI Mak, RP Martins 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 270-272, 2019 | 88 | 2019 |
| A 10.6-mW 26.4-GHz dual-loop type-II phase-locked loop using dynamic frequency detector and phase detector Z Yang, Y Chen, S Yang, PI Mak, RP Martins IEEE Access 8, 2222-2232, 2019 | 22 | 2019 |
| A m2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4–44 GHz) Y Chen, Z Yang, X Zhao, Y Huang, PI Mak, RP Martins IEEE Solid-State Circuits Letters 2 (5), 37-40, 2019 | 22 | 2019 |
| A 3.3-GHz integer N-type-II sub-sampling PLL using a BFSK-suppressed push–pull SS-PD and a fast-locking FLL achieving− 82.2-dBc REF spur and− 255-dB FOM Z Yang, Y Chen, J Yuan, PI Mak, RP Martins IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (2), 238-242, 2021 | 19 | 2021 |
| A calibration-free, reference-buffer-free, type-I narrow-pulse-sampling PLL with− 78.7-dBc REF spur,− 128.1-dBc/Hz absolute in-band PN and− 254-dB FOM Z Yang, Y Chen, PI Mak, RP Martins IEEE Solid-State Circuits Letters 3, 494-497, 2020 | 19 | 2020 |
| A 0.003-mm² 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Z Yang, Y Chen, PI Mak, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers, 2021 | 16 | 2021 |
| A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis Y Chen, PI Mak, Z Yang, CC Boon, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers 66 (10), 3991-4004, 2019 | 10 | 2019 |
| A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Z Yang, Y Chen, PI Mak, RP Martins 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 283-284, 2019 | 6 | 2019 |
| A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving− 80-dBc Reference Spur and− 259-dB FoM with 12-pF Input Load Z Yang, M Osada, S Li, Y Zhu, T Iizuka 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 1 | 2023 |
| A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving− 63-dBc Reference Spur, 175-fs RMS Jitter and− 240-dB FOMjitter Z Yang, Z Xu, M Osada, T Iizuka 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 1 | 2022 |
| A 6-GHz 78-fs Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving 92-dBc Reference Spur and 258-dB FOM H Ren, Z Yang, Y Huang, C Feng, T Chen, X Zhang, X Meng, W Yan, ... IEEE Microwave and Wireless Technology Letters, 2024 | | 2024 |
| 7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur Y Huang, Y Chen, Z Yang, RP Martins, PI Mak 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 130-132, 2024 | | 2024 |
| A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering M Osada, Z Xu, Z Yang, T Iizuka IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
| Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit Z Cheng, Z Yang, Y Zhu, MS Sarker, H Yamahara, M Seki, H Tabata, ... 2023 International Conference on IC Design and Technology (ICICDT), 92-95, 2023 | | 2023 |
| A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit Y Zhu, Z Yang, Z Cheng, MS Sarker, H Yamahara, M Seki, H Tabata, ... 2023 International Conference on IC Design and Technology (ICICDT), 88-91, 2023 | | 2023 |
| Power-Efficient RF and mm-Wave VCOs/PLL H Guo, Z Yang, CC Lim, H Ramiah, Y Peng, Y Chen, J Yin, PI Mak, ... Analog and Mixed-Signal Circuits in Nanoscale CMOS, 51-89, 2023 | | 2023 |
| Investigation and Improvement on Self-dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis Y Zhu, Z Yang, M Osada, H Zhang, T Iizuka IEICE Transactions on Fundamentals of Electronics, Communications and …, 2023 | | 2023 |
Pui-In Mak (Elvis)Professor at University of Macau | IEEE Fellow | IET Fellow | RSC Fellow | CAS Overseas ExpertVerified email at umac.mo
