3D-MAPS: 3D Massively parallel processor with stacked memory DH Kim, K Athikulwongse, M Healy, M Hossain, M Jung, I Khorosh, ...
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 …, 2012
218 2012 TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC M Jung, J Mitra, DZ Pan, SK Lim
Communications of the ACM 57 (1), 107-115, 2014
166 2014 Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory MB Healy, K Athikulwongse, R Goel, MM Hossain, DH Kim, YJ Lee, ...
Proc. of CICC, 2010
98 2010 Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory) DH Kim, K Athikulwongse, MB Healy, MM Hossain, M Jung, I Khorosh, ...
IEEE Transactions on Computers 64 (1), 112-125, 2013
78 2013 TSV stress-aware full-chip mechanical reliability analysis and optimization for 3-D IC M Jung, J Mitra, DZ Pan, SK Lim
IEEE Transactions on Computer-aided design of integrated circuits and …, 2012
59 2012 A study of IR-drop noise issues in 3D ICs with through-silicon-vias M Jung, SK Lim
2010 IEEE International 3D Systems Integration Conference (3DIC), 1-7, 2010
47 2010 Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC M Jung, X Liu, SK Sitaraman, DZ Pan, SK Lim
Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on …, 2011
46 2011 Design for Manufacturability and Reliability for TSV-based 3D ICs DZ Pan, SK Lim, K Athikulwongse, M Jung, J Mitra, J Pak, M Pathak, ...
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific …, 2012
37 2012 On enhancing power benefits in 3D ICs: Block folding and bonding styles perspective M Jung, T Song, Y Wan, Y Peng, SK Lim
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
33 2014 Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts A Ceyhan, M Jung, S Panth, SK Lim, A Naeemi
IEEE International Interconnect Technology Conference, 345-348, 2014
29 2014 How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core M Jung, T Song, Y Wan, YJ Lee, D Mohapatra, H Wang, G Taylor, ...
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013
24 2013 A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs J Mitra, M Jung, SK Ryu, R Huang, SK Lim, DZ Pan
2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 746-753, 2011
24 2011 Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs M Jung, DZ Pan, SK Lim
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, 317-326, 2012
22 2012 Impact of mechanical stress on the full chip timing for through-silicon-via-based 3-D ICs K Athikulwongse, JS Yang, DZ Pan, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
21 2013 Chip/package mechanical stress impact on 3-D IC reliability and mobility variations M Jung, DZ Pan, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
16 2013 Design methodologies for low-power 3-D ICs with advanced tier partitioning M Jung, T Song, Y Peng, SK Lim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (7 …, 2017
14 2017 Evaluating Chip-Level Impact of Cu/Low- A Ceyhan, M Jung, S Panth, SK Lim, A Naeemi
IEEE Transactions on Electron Devices 62 (3), 940-946, 2015
14 2015 A study of TSV variation impact on power supply noise M Jung, S Panth, SK Lim
2011 IEEE International Interconnect Technology Conference, 1-3, 2011
11 2011 Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs K Athikulwongse, DH Kim, M Jung, SK Lim
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 687-692, 2013
10 2013 Thermal impact study of block folding and face-to-face bonding in 3D IC Y Peng, M Jung, T Song, Y Wan, SK Lim
2015 IEEE International Interconnect Technology Conference and 2015 IEEE …, 2015
6 2015 
Sung Kyu LimProfessor, Georgia Institute of TechnologyAdresse e-mail validée de ece.gatech.edu
