Javier Mora
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Self-reconfigurable evolvable hardware system for adaptive image processing
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
IEEE Transactions on Computers 62 (8), 1481-1493, 2013
522013
Fault tolerance analysis and self-healing strategy of autonomous, evolvable hardware systems
R Salvador, A Otero, J Mora, E de la Torre, L Sekanina, T Riesgo
2011 International Conference on Reconfigurable Computing and FPGAs, 164-169, 2011
362011
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems
A Otero, R Salvador, J Mora, E de la Torre, T Riesgo, L Sekanina
2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 336-343, 2011
232011
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 184-191, 2011
182011
Implementation techniques for evolvable HW systems: Virtual vs. dynamic reconfiguration
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
2012 22nd International Conference on Field Programmable Logic and …, 2012
142012
A novel FPGA-based evolvable hardware system based on multiple processing arrays
A Gallego, J Mora, A Otero, R Salvador, E de la Torre, T Riesgo
Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW …, 2013
132013
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs
J Mora, A Otero, E de la Torre, T Riesgo
2015 10th International Symposium on Reconfigurable Communication-centric …, 2015
122015
A scalable evolvable hardware processing array
A Gallego, J Mora, A Otero, E de la Torre, T Riesgo
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference …, 2013
92013
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado
R Zamacola, AG Martínez, J Mora, A Otero, E de La Torre
2018 International Conference on ReConFigurable Computing and FPGAs …, 2018
52018
A noise-agnostic self-adaptive image processing application based on evolvable hardware
J Mora, A Gallego, A Otero, B López, E de la Torre, T Riesgo
2013 Conference on Design and Architectures for Signal and Image Processing …, 2013
52013
Accelerating the evolution of a systolic array-based evolvable hardware system
J Mora, E de la Torre
Microprocessors and Microsystems 56, 144-156, 2018
42018
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform
J Mora, Á Gallego, A Otero, E de la Torre, T Riesgo
2013 Conference on Design and Architectures for Signal and Image Processing …, 2013
32013
A self-adaptive image processing application based on evolvable and scalable hardware
Á Gallego, J Mora, A Otero, B López, E de la Torre, T Riesgo
2013 23rd International Conference on Field programmable Logic and …, 2013
32013
On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming
J Mora, R Salvador, E de la Torre
Genetic Programming and Evolvable Machines, 1-32, 2018
12018
Prospection of Reconfiguration Capabilities using Space Qualified SRAM-based FPGAs for a Satellite Communications Application
F Veljković, J Mora, T Riesgo, E de la Torre, LB Valero, RR Sánchez, ...
31st AIAA International Communications Satellite Systems Conference, 5683, 2013
12013
Evolvable hardware FPGA-based platform for autonomous fault-tolerant systems
A Otero, J Mora, R Salvador, Á Gallego, E de la Torre, L Sekanina
2012 International Conference on ReConFigurable Computing and FPGAs …, 2012
12012
Architecture and methodology for automated development of evolvable and reconfigurable hardware applications
J Mora de Sambricio
Industriales, 2019
2019
A Dynamically Adaptable Image Processing Application Trading Off Between High Performance, Consumption and Dependability in Real Time
J Valverde Alcalá, A Rodríguez Medina, J Mora de Sambricio, ...
Industriales, 2014
2014
Increased fault tolerance in evolvable hardware through automatic upscaling
J Mora, Á Gallego, A Otero, E de la Torre, T Riesgo
Cei, 2014
2014
Development of Brain-Computer Interfaces using Evolvable Hardware
B López, J Mora, P Mansanet, E Torre Arnanz, T Riesgo Alcaide
IEEE, 2014
2014
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