Lukas Sekanina
Lukas Sekanina
Professor of Computer Science and Engineering, Brno University of Technology
Adresse e-mail validée de fit.vutbr.cz - Page d'accueil
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Evolvable components: from theory to hardware implementations
L Sekanina
Springer Verlag, 2004
173*2004
Efficient recognition of speed limit signs
J Torresen, JW Bakke, L Sekanina
Proceedings. The 7th International IEEE Conference on Intelligent …, 2004
1412004
Virtual reconfigurable circuits for real-world applications of evolvable hardware
L Sekanina
International Conference on Evolvable Systems, 186-197, 2003
1322003
Evoapprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods
V Mrazek, R Hrbacek, Z Vasicek, L Sekanina
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
1182017
Evolutionary approach to approximate digital circuits design
Z Vasicek, L Sekanina
IEEE Transactions on Evolutionary Computation 19 (3), 432-444, 2014
862014
Design of power-efficient approximate multipliers for approximate artificial neural networks
V Mrazek, SS Sarwar, L Sekanina, Z Vasicek, K Roy
Proceedings of the 35th International Conference on Computer-Aided Design, 1-7, 2016
822016
Novel hardware implementation of adaptive median filters
Z Vasicek, L Sekanina
2008 11th IEEE workshop on design and diagnostics of electronic circuits and …, 2008
762008
An evolvable hardware system in Xilinx Virtex II Pro FPGA
Z Vasicek, L Sekanina
International Journal of Innovative Computing and Applications 1 (1), 63-73, 2007
732007
Image filter design with evolvable hardware
L Sekanina
Workshops on Applications of Evolutionary Computation, 255-266, 2002
712002
Towards evolvable systems based on the Xilinx Zynq platform
R Dobai, L Sekanina
2013 IEEE international conference on evolvable systems (ICES), 89-95, 2013
602013
An evolvable combinational unit for FPGAs
L Sekanina, Š Friedl
Computing and informatics 23 (5-6), 461-486, 2004
602004
Evolutionary design of arbitrarily large sorting networks using development
L Sekanina, M Bidlo
Genetic Programming and Evolvable Machines 6 (3), 319-347, 2005
582005
Evolutionary design of gate-level polymorphic digital circuits
L Sekanina
Workshops on Applications of Evolutionary Computation, 185-194, 2005
582005
Self-reconfigurable evolvable hardware system for adaptive image processing
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
IEEE transactions on computers 62 (8), 1481-1493, 2013
572013
Towards evolvable IP cores for FPGAs
L Sekanina
NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings., 145-154, 2003
542003
Physical demonstration of polymorphic self-checking circuits
R Ruzicka, L Sekanina, R Prokop
2008 14th IEEE International On-Line Testing Symposium, 31-36, 2008
532008
An evolvable image filter: Experimental evaluation of a complete hardware implementation in fpga
T Martínek, L Sekanina
International Conference on Evolvable Systems, 76-85, 2005
532005
Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware
Z Vasicek, L Sekanina
Genetic Programming and Evolvable Machines 12 (3), 305-327, 2011
522011
Repomo32-new reconfigurable polymorphic integrated circuit for adaptive hardware
L Sekanina, R Ruzicka, Z Vasicek, R Prokop, L Fujcik
2009 IEEE Workshop on Evolvable and Adaptive Hardware, 39-46, 2009
512009
Detection of Norwegian Speed Limit Signs.
L Sekanina, J Tørresen
ESM, 337-340, 2002
482002
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