Dong Hyuk Woo
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An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth
DH Woo, NH Seong, DL Lewis, HHS Lee
High Performance Computer Architecture (HPCA), 2010 IEEE 16th International …, 2010
Extending Amdahl's law for energy-efficient computing in the many-core era
DH Woo, HHS Lee
Computer 41 (12), 24-31, 2008
Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping
NH Seong, DH Woo, HHS Lee
ACM SIGARCH Computer Architecture News 38 (3), 383-394, 2010
SAFER: Stuck-at-fault error recovery for memories
NH Seong, DH Woo, V Srinivasan, JA Rivers, HHS Lee
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 115-124, 2010
3D-MAPS: 3D massively parallel processor with stacked memory
SK Lim, SK Lim
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits …, 2013
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory
MB Healy, K Athikulwongse, R Goel, MM Hossain, DH Kim, YJ Lee, ...
Custom Integrated Circuits Conference (CICC), 2010 IEEE, 1-4, 2010
Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory)
DH Kim, K Athikulwongse, MB Healy, MM Hossain, M Jung, I Khorosh, ...
IEEE Transactions on Computers 64 (1), 112-125, 2013
Neural network compute tile
O Temam, R Narayanaswami, H Khaitan, DH Woo
US Patent 9,710,265, 2017
SIMD divergence optimization through intra-warp compaction
AS Vaidya, A Shayesteh, DH Woo, R Saharoy, M Azimi
Proceedings of the 40th Annual International Symposium on Computer …, 2013
Analyzing performance vulnerability due to resource denial of service attack on chip multiprocessors
DH Woo, HH Lee
Workshop on Chip Multiprocessor Memory Systems and Interconnects, 2007
Systems and methods providing wear leveling using dynamic randomization for non-volatile memory
NH Seong, DH Woo, HHS Lee
US Patent 8,806,171, 2014
COMPASS: a programmable data prefetcher using idle GPU shaders
DH Woo, HHS Lee
ACM SIGPLAN Notices 45 (3), 297-310, 2010
Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU
D Kim, S Lee, J Chung, DH Kim, DH Woo, S Yoo, S Lee
Proceedings of the 49th Annual Design Automation Conference, 888-896, 2012
Neural network accelerator with parameters resident on chip
O Temam, H Khaitan, R Narayanaswami, DH Woo
US Patent 10,504,022, 2019
Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor
AS Vaidya, A Shayesteh, DH Woo, S Saharoy, M Azimi
US Patent 9,606,797, 2017
Security refresh: Protecting phase-change memory against malicious wear out
NH Seong, DH Woo, HH Lee
IEEE micro 31 (1), 119-127, 2010
Accessing data in multi-dimensional tensors
DH Woo, AE Phelps
US Patent 9,875,104, 2018
Exploiting input data sparsity in neural network compute units
DH Woo, R Narayanaswami
US Patent 9,818,059, 2017
Reducing energy of virtual cache synonym lookup using bloom filters
DH Woo, M Ghosh, E Özer, S Biles, HHS Lee
Proceedings of the 2006 international conference on Compilers, architecture …, 2006
Neural network instruction set architecture
R Narayanaswami, DH Woo, O Temam, H Khaitan
US Patent 9,836,691, 2017
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